The DSP's PCI is connected to the bridge. The DSP has an external PCI configuration EEPROM loaded during POR. Both bridge and DSP are located on a board connected to the backend. The board is powered 1st and only then the Backend
Based on the DSP spec., the PCI clock should be ready before the POR is de-asserted. However, the PCI clock, provided by the XIO2001, is active only when the PCI-e reset is de-asserted, in our case seconds after the POR is de-asserted. What I can't understand is how the board is being recognized correctly during enumeration with Vendor ID etc.
Meir
