SN65DP159: Power on sequence of SN65DP159

shiwei luan

Part Number: SN65DP159

Hi, I attached the captures of power on timing section of DP159.

Figure 22 is confusing to me: why there is VCC/VDD, and VDD/VCC? How to understand td1? Is there a specific timing requirement of VCC and VDD on which should ramp first?

td1 is specified at max = 200us. If I apply VCC first, then VDD must start ramping within 200us?

From this thread, there is no requirement of sequence VCC, VDD as long as OE is LOW.

e2e.ti.com/.../672347

Thank you.

over 7 years ago

0 Malik Barton57 over 7 years ago

TI__Guru 64326 points

Shiwei,

Figure 22 shows that the order in which Vdd/Vcc rises does not matter but once one rises the other should rise within 200 us of Vcc. This is in the case when OE is being controlled externally. If there is a passive reset (i.e. external cap) Vdd must be stable before Vcc.

0 shiwei luan over 7 years ago in reply to Malik Barton57

Intellectual 750 points

If VCC is first stable, then VDD is stable 5seconds later, but OE is always LOW until both are stable, will it cause any problem?

Thank you.

0 Malik Barton57 over 7 years ago in reply to shiwei luan

TI__Guru 64326 points

Shiwei,

Since the timing in the figure is out of spec occurring to the datasheet we cannot guarantee device performance.

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SN65DP159: Power on sequence of SN65DP159