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DP83822H: Reset timing requirements

Georg Waibel
Prodigy 20 points

Part Number: DP83822H

Hi,

I am trying to understand the Reset timing requirements of the DP83822 PHY (datasheet chapter 7.7 and figure 2).

1) When deasserting the RESET pin, the host shall wait >2ms (T2) befor issuning a command via MDI. Is this correct?

2) The hardware configuration latch-in time (T3) is typ. 120ms?! Does this mean that reading in the pin-strapping configuration takes such a long time? Do I need to wait for this time until the PHY is ready? If so, a mximum value should be specified, not a typical one. Or is there a MDI register which I can read to check if configuration has been finished? How could I access the PHY if strapping-in the MDI address is not yet finished (there are multiple PHYs at the MDI)?

3) I checked the DP83822 driver (dp83822.c) in the Linux kernel source code. Function dp83822_phy_reset() issues a reset request (set bit15 in register 0x1F). Then it reads the BMSR without any delay time. Should there not be any delay time? At least the 2ms (T2) delay?

Thanks and regards

Georg Waibel

  • 0
    TI__Mastermind 19780 points
    Hi Georg,

    1. Yes.

    2. Yes, the time is 120ms. The actual time is much less than this, but was not characterized in development, so we can't guarantee a shorter time in the DS. If you want, you can read back register address 0x2 and when a valid response of 0x2000 is received, the PHY is ready.

    3. The driver should have some delay... the actual reset time is much lower than the 2ms stated in the DS, so no problems are likely to be run into regarding the amount of time it takes Linux to execute the next line.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 20 points

    Hi Rob,

    thanks for the clarification. We got the PHY running now...

    Georg