DP83822I: About TX_CLK Phase shift for MII in DP83822I

Hi Kevin,

There appears to be a lot of reflections in your TX_CLK waveform. Where are you probing the waveform? Is the MAC active at this time? Is the signal properly terminated in a 50 ohm load?

The phase shift in the register should not be affecting what the waveform looks like.

Can you share a schematic?

Best Regards,

Hi  Rob,

It seems that MAC is active  because there is MDC and MDIO signal. What does the meaning of "Is the signal properly terminated in a 50 ohm load?" I only put a 21.5 ohm serial resistor between PHY and MAC.

Attachment is my schematic. Though there is no strapping configuration in my schematic, I have flied wires for MII strapping configuration.

453564703941-A-SCHM_C 5.pdf

Hi Rob,
I found another issue about Tx_CLK and Tx_Data in MII mode, whose setup time was measured as 6~8ns,which is smaller than 10ns defined in DP83822's datasheet. Is this cause for the issue of no linking? Thank you!

Hi Rob,
I want to implement one thing,
I grouped TX including TX_CLK, TX_CTRL and TX_D[3:0], while I grouped RX including RX_CLK, RX_DV,RX_ER, RX_D[3:0], and I controlled all traces impedance as 50 ohm except for the differential pairs as 100 ohm.

Hi Rob,
In my board, SPL can be downloaded through PHY successfully and I triggered debugging signal DEBUG_TXD when SPL was downloading through PHY, then find the TX_CLK is normal. But when 1st phase is finished, the TX_CLK is abnormal, which will has changing high voltage level from 2.6V to 4.1V. So what the root cause of the TX_CLK? Is there something wrong with hardware configuration in my design? Thanks!

Is anybody here who can support this issue?