SN65DP159: About SN65DP159 AUX_SRCP/AUX_SRCN output

Vera Mao

Part Number: SN65DP159

hi dear supporting team,

when operating at Displayport mode, how is the clk output from AUX_SRCP/AUX_SRCN generated? which signals/factors does it relate with? tks!

over 7 years ago

0 JMMN over 7 years ago

TI__Guru 60870 points

The clock on AUX is a divided down version of the clock feeding the OUT channels of the DP159.

Regards,
JMMN

0 Vera Mao over 7 years ago in reply to JMMN

TI__Expert 5065 points

hi JMMN,

Could you pls help explain what do you mean by "out" channel? it seems all of them are output channel. there is a PLL inside the chip, is the clk related with the PLL? it will be much appreciate that you could help provide the CLK block diagram. tks a lot!

0 Malik Barton57 over 7 years ago

TI__Guru 64326 points

Vera,

SN65DP159 generates the clock from the data see on OUT [3:0]. If there is jitter in the data (generated from source or SN65DP159) on OUT[3:0] this will affect the clock output.

0 Vera Mao over 7 years ago in reply to Malik Barton57

TI__Expert 5065 points

hi Malik,
thanks for the reply!
here is one more question on AUX_SRC, Before the link training is finished, how about the output frequency from this port? tks a lot!

0 JMMN over 7 years ago in reply to Vera Mao

TI__Guru 60870 points

Hi Vera,

The clock on the AUX pins will not be valid until LOCK_COMPLETE is set indicating the PLL has locked.

Regards,
JMMN

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SN65DP159: About SN65DP159 AUX_SRCP/AUX_SRCN output