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DP83867IR: What is the threshold value of XI at VDDIO=3.3V ?

user5163865
Genius 3980 points
Part Number: DP83867IR
Other Parts Discussed in Thread: ADS1255

Hi,

Our customer have a question.

Since XI is a 1.8 V input regardless of VDDIO, the customer divides the 3.3 V clock source with C1, C2 (according to D/S P111 fig.31).

When C1 = C2 = 27 pF, the 3.3 V clock amplitude is 1.65 V.

Question: What is VIH, VIL in this case?

Should we follow the specification of VDDIO = 1.8 V?
However, since VIH = 1.8 V * 0.7 = 1.26 V, I think that it can not be used with a 2.5 V clock source (1.25 V = equally divided).

Best regards

Hiroshi

  • 0
    TI__Mastermind 18425 points
    Hello Hiroshi,

    The Vih Vil is not mentioned in the datasheet so we may not be able to share this information. Can you share how this information will be used in the design?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Genius 3980 points

    Hi Aniruddha,

    Thank you for your reply.

    Customer's design is below.

    SG-211SCE(3.3V)　→　74FCT38074SDCGI（3.3V)　→　Cap divider (27pF）　→　DP83867IR : X_I
    Xtal OSC                          1 to 4 clock buffer

    *note
    74FCT38074SDCGI at Vdd=3.3V

    Output 
    High Min：2.2V＠25mA  Low Max：0.7V＠25mA

    Actually, Output Hi  is almost 3.3V. @over temp range

    Customers said OK if TI guarantees the operation of this condition.

    If clear specifications can not be presented, can TI guarantee this?

    I do not know the OSC driver of DP83867 in detail,
    If OSC can be driven directly, I think that it has a very low threshold.

    Therefore, I think that this requirement is sufficiently easy level.

    Since this application has design review by end users, evidence / guarantee is necessary for unknown specifications.

    I will wait for your reply.


    Best regards,

    Hiroshi

  • 0 in reply to user5163865
    TI__Mastermind 18425 points
    Hi Hiroshi,

    Let me review our internal data and check if we can provide more information about this topic. I will try to get an update by 07/30.

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Genius 3980 points

    Hi Aniruddha,

    Thank you for your reply.
    If Xtal and CLK input are the same condition, I think that it is no problem even if clear specifications are not known. So I will report it to the customer.
    However, as with the ADS1255, there is a product with a high threshold at the time of CLK input, so TI's judgment is necessary.

    Best regards,
    Hiroshi

  • 0 in reply to user5163865
    TI__Mastermind 18425 points
    Hi Hiroshi,

    Since customer is using 3.3V oscillator, a 27pF capacitor divider is ok. Vih (min) will be ~1.4V. Vil (max) will be 0.45V.

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Genius 3980 points

    Hi Aniruddha,

    I am grateful for your support.

    Best regards,

    Hiroshi