Based on Table 5 of the datasheet I have open Rhi and Rlo resistors on RX_D0 and RX_D2 which should equate to Mode 1 and a phy address of 0x0. The only other connection to the RX data lines is a Xilinx US+ FPGA. When I read the strapping data from STRAP_STS1 I see that the address strapping detected is 0x5 (equates to Mode 2 on the pins). My VDDIO is 1.8V.
Will the FPGA loading cause this mode change?
Thanks,
-Allan
