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PCA9306: Is there a condition falling malfunction?

Toshihiro Watanabe
Genius 10235 points
Part Number: PCA9306

Hello,

Is there a malfunction situation when power up or power down when we configure figure 7 of the datasheet?

VREF2 pin capacitor charge and discharge are delayed due to time constant of 200kohm and capacitor value.

When power cycle which very short VREF2 OFF time duration happens, VREF2 capacitor may still have voltage due to this time constant.

In this case, VREF1 side condition doesn't define but is there a condition which PCA9306 falls malfunction condition?

There were devices to define power cycle requirement for POR. For example, next power up should be done after power supply voltage becomes less than 0.5V for example. I would like to confirm if PCA9306 doesn't fall unstable state when power cycle is applied medium power supply voltage.

Best regards,

Toshihiro Watanabe 

  • 0
    TI__Guru 73491 points
    Hello Toshihiro-san,

    "In this case, VREF1 side condition doesn't define but is there a condition which PCA9306 falls malfunction condition?"

    You need to make sure Vref1 powered on before Vref2 otherwise the device will establish a higher reference voltage and cause the path between side 1 and side 2 to be low impedance. If Vcc1 is GND then the internal switch will close and result in a voltage divider on SDA/SCL.

    -Bobby
  • 0 in reply to BOBBY
    TI__Genius 10235 points
    Hello Bobby-san,
    I think this operation is PCA9306 is working correctly because device is enable and Vref1 side logic is low.
    Can we think ok PCA9306 is MOSFET switch so PCA9306 doesn't become abnomal mode? We need noticed VREF2 side becomes low when VREF1 < VREF2 condition happens, this is only limitation?
    Best regards,
    Toshihiro Watanabe
  • 0 in reply to Toshihiro Watanabe
    TI__Guru 73491 points
    Hello Toshihiro-san,

    "Can we think ok PCA9306 is MOSFET switch so PCA9306 doesn't become abnomal mode?"
    Yes, you can think of it in that way.

    "We need noticed VREF2 side becomes low when VREF1 < VREF2 condition happens, this is only limitation?"
    If you are using configuration in figure 7 then the only requirement in terms of power sequencing is that Vref1 turns on before Vref2.

    -Bobby
  • 0 in reply to BOBBY
    TI__Genius 10235 points
    Hello Bobby-san,
    Thank you for your answer.
    The customer want to know how we determine the capacitor value of VREF2 pin. He thinks increasing this capacitor value is no issue if we can wait to start communication till cap value is full charged. Do you agree with his idea.
    I think it is better to use recommendation value, 100pF though.
    Best regards,
    Toshihrio Watanabe
  • 0 in reply to Toshihiro Watanabe
    TI__Guru 73491 points
    Hi Toshihiro-san,

    "He thinks increasing this capacitor value is no issue if we can wait to start communication till cap value is full charged. Do you agree with his idea."
    -He can do this, putting another capacitor in parallel with the recommended 100pF can work. As long as he waits for the Vref2 to fully charge before starting I2C communication then it will be fine.

    Thanks,
    -Bobby