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TCA9800: VOL on the B side difference TCA9800 vs TCA9517

Part Number: TCA9800
Other Parts Discussed in Thread: TCA9517, , TCA9509

Hello team,

It may be a fundamental question, but could you instruct me about VOL on the B side difference TCA9800 vs TCA9517?
I found the following sentence on the application report(SLVA878: www.ti.com/.../slva878.pdf) and wonder what is the key point from the device internal structure point of view or I2C application specific reason.

"This VOL and VIL mis-match is common, especially when a buffer device with a voltage offset is used. Most
of these common buffers will have a fixed VOL output of 0.5 V. The TCA980x helps with these issues by
providing a very low VOL signal on both the A and B sides. The A-side typical value is below 0.1 V and the
B side typical VOL is 0.2 V"

My questions are;

1) Why most of the buffers(such as TCA9517) have VOL output offset of 0.5V?

2) Why the VOL offset is generated only on the B side?

3) What is the main reason why TCA9800 can sustain lower VOL?

Thanks in advance.
Shinya Sawamoto

  • Hello Shinya-San,

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    "1) Why most of the buffers(such as TCA9517) have VOL output offset of 0.5V?"

    -So this question is a little tricky. There is a trade off for having a higher VoL offset and a lower one. I2C/SMBUS standards state that a pull down FET should have a VoL of 0.4V if it is sinking 3mA of current so choosing a static voltage offset larger than 0.4V is beneficial.

    One key thing with devices which use a static voltage offset is the ViLc parameter which states you must pull lower than this value in order to pass a low from the static offset side to the A side. This is important when A side is pull B side down and generating the VoL on B side but B side needs to pass a low back to A side immediately. (This kind of thing occurs during the data line handoff like an ACK event where the master may have sent a 0 as bit 8 and has control of the data line while the slave needs to acK during the 9th clock pulse so they need to exchange control of the data line). If the device on B side does not pull below ViLc then there is a chance it can miss sending data to A side (master/slave could miss an ACK because of this).

    If you set a higher static voltage offset it means you can have a higher ViLc (ViLc must always be lower than the static voltage offset ex. if offset is 700mV then ViLc can be 500mV but not above 700mV). The disadvantage of a large static voltage offset is in cases where master/slave use a lower Vcc such as 1.8V. ViL of the master/slave is 30% of Vcc or in this example 540mV. If your static voltage offset is above 540mV then the master or slave may never see a low.

    Using a lower static voltage offset can help with communicating with slaves/masters with lower Vcc's but then it will result in a lower ViLc. In a heavily loaded I2C bus, using a strong pull up resistor is necessary but will result in a larger VoL from a master/slave and if this VoL is larger than ViLc then it means you cannot reliably send lows (ACKs) across the buffer.

    In summary, 500mV as a static voltage offset is a good median/voltage inorder to communicate to lower logic devices (devices with lower Vcc) and makes it easier for master/slaves to generate a VoL which is lower than ViLc to reliably communicate across the buffer during ACK events.

    "2) Why the VOL offset is generated only on the B side?"

    -This is not always the case, we do have a device (TCA9509) which has the offset side on A side. The industry kind of sees B side as the common side to make the offset and B side also typically is connected to the higher logic voltages (higher Vcc) so the industry likes to do this. (remember higher logic/Vcc means ViL of master/slave is more likely to see the voltage offset to be below ViL of the master/slave).

    Ultimately, it is not an industry rule or part of a standard but the designers of the devices seem to just do it on B side more often than not. Some devices do use the offset side on A side though.

    3) What is the main reason why TCA9800 can sustain lower VOL?

    The fundamental difference between these two buffers (TCA9800 and TCA9517) is actually how they generate the VoL and how they detect a low.

    TCA9517 uses a static voltage offset generated by forward conducting diodes which is pretty straight forward.

    TCA9800 uses an internal current source and monitors if the current is being sourced out or being sunk internally using current monitoring. When A side pulls low, B side's pull down FET turns on and sinks the current which is always constant. The Rdson of B side FET is low enough such that the current x Rdson results in a typical VoL of 0.2V

    To summarize, TCA9800 uses a pull down FET with a low Rdson to sink its own current. TCA9517 uses diodes to generate the static voltage offset. Two different methods with two different results.

    I hope my explanation is clear.

    -Bobby

    Please note we also have a new app note discussing why devices needs a static voltage offset written by our senior I2C applications engineer .

    This app note is very though and should provide you with more insight about how buffers work.

  • Thank you so much for your dedicated support, Bobby.
    It will help me a lot to learn more about I2C common matters although I'm not familiar with it.

    Regards,
    Shinya Sawamoto