• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 35 subscribers
  • Views 571 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB914A-Q1: Glitch on PCLK Output During Power-Up

Kenichiro
Mastermind 9165 points
Part Number: DS90UB914A-Q1


[ DS90UB914A-Q1 ] Glitch on PCLK Output During Power-Up

Hi,

My customer has found that the glitch on PCLK output can be seen during ramp-up.
Is this expected?



CH1: VDDIO
CH2: VDD_n
CH3: PDB
CH4: PCLK(No load connected on PCLK pin)

Thanks,
Ken

  • 0
    TI__Genius 10475 points
    Ken,
    Is this on the EVM? What is the source of the reference clock on the serializer side?
    What is the PCLK frequency?
    The PDB is not asserted after the supply ramp based on this measurement. Please refer to the 914A datasheet for power up and PDB requirements.
  • 0 in reply to Palaniappan Manickam
    Mastermind 9165 points

    Pal,

    This can be seen on customer board, however I know that LVCMOS Output has this kind of glitch issue, please check with your team internally.
    That was for GPIOx pins, it's helpful, if you can check this glitch can be seen on PCLK pin as well.

    Thanks,
    Ken

  • 0 in reply to Kenichiro
    TI__Intellectual 2930 points
    This can happen depending on how different power supplies get into the device. We do not expect any issue for our device due to this glitch. During the initial powerup stages different LVCMOS pins could transition. Recommended sequencing is once power supplies ramp up and are settled, PDB pin is transitioned. If things follow this specific sequence you should not see glithcing
  • 0 in reply to Vijaya Ceekala
    Mastermind 9165 points

    Hi Vijaya,

    Thank you for sharing the information.
    I understood that this kind of glitch on LVCMOS pins would not damage DS90UB914A-Q1.

    My customer is concerned that this potentially damages the pins which are connected to LVCMOS pins of DS90UB914A-Q1.

    Here I attach their findings with signal name. As you can see, during power-ramp, they put PDB signal low, however the glitch still can be seen.
    Is this what you expect?



    Thanks,
    Ken