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DP83822H: About Reset Timing

Kenji Ohno1
Genius 5095 points
Part Number: DP83822H


Hi Team,

Figure 2. For Reset Timing, T2 is specified as 2ms (max).

At Rev. A (SNLS 505 A), it was 195 ms typ.Is Max 2. ms of Rev. C correct?

Another, T1's NOTES "X1 clock must be stable for a minimum of 1 μs during RESET pulse low time"

Does this means that XI needs to stabilize within 1 μs after the RESET pulse changes to L?

Best Regards,

Kenji

  • 0
    TI__Mastermind 23675 points
    Hi Kenji,

    The updated version is correct.
    What the clock stabilization time is saying is that for RESET to occur properly the reference clock needs to be stable for at least 1uS during while RESET is LOW.
  • 0 in reply to Ross Pimentel
    Genius 5095 points
    Hi Ross,

    Thank you for answering.
    Is there a minimum for Reset Timing's T2? How many should Typ value be targeted?
    Although Power - Up Timing is specified as T2 = 200 ms (max), is it also necessary to wait for a RESET pulse to be applied after the power is turned on?

    Another thing, there is no MDIO waveform in Figure 2.
    What kind of waveform is correct for MDIO?
    Is there a waveform?

    Best Regards,
    Kenji
  • 0 in reply to Kenji Ohno1
    TI__Mastermind 23675 points
    Hi Kenji,

    There is no minimum. You should not try and access MDIO/MDC until the 2ms expires. That is the reason why there is no typ or min value listed.
    For POR, there is no need for you to apply a RESET. This is done internally by the PHY. All you need to do is wait 200ms before accessing MDIO/MDC.

    MDC is just a clock waveform at whatever frequency you are operating it at.
    MDIO is just a toggling CMOS line with whatever pattern you are transmitting or receiving.
    This bus timing image here is a good example: en.wikipedia.org/.../Output