DP83867E: DP83867E

Ben Manor

Prodigy 50 points

Part Number: DP83867E

Hi,

I'm interfacing the DP83867E to a XILINX ZYNQ FPGA.

The DP83867E PHY sends to the FPGA a 625MHz clock over the SGMII CLK pair (SGMII_COP, SGMII_CON).

Is this a fixed frequency according to SGMII spec or can it be configured?

Thanks,

Ben Manor

Astronautics

over 7 years ago

0 Geet Modi over 7 years ago

TI__Mastermind 26320 points

Hi,

SGMII frequency is fixed.

Regards,
Geet

0 Ben Manor over 7 years ago in reply to Geet Modi

Prodigy 50 points

Hi,

Can the CLK_OUT output be configured to output a fixed 125 MHz reference clock? (regardless of the actual Ethernet rate)

This then can be used as the FPGA's SGMII REF CLK.

Thanks

Ben Manor

0 Geet Modi over 7 years ago in reply to Ben Manor

TI__Mastermind 26320 points

Hi Ben,

Yes, DP83867 provide mulitple options for clock-output. It includes recovered clock, recovered clock/5 , transmit clock, XI etc.

For your case, you can use Transmit Clock which is generate by local PLL and not dependent on the link rate.

Regards,
Geet

0 Ben Manor over 7 years ago in reply to Geet Modi

Prodigy 50 points

Hi Geet,

Thanks for your helpful support.

Just to clearly understand:

The CLK_OUT can be configured to output a continuous 125 MHz reference clock regardless of the link rate.

What would be the setting of the I/O Configuration register (address 0x0170) in that case?

Ben Manor

0 Geet Modi over 7 years ago in reply to Ben Manor

TI__Mastermind 26320 points

Hi ,

You can use "Channel A transmit clock"

Regards,
Geet

0 Ben Manor over 7 years ago in reply to Geet Modi

Prodigy 50 points

Much Obliged.

we'll do that.

Ben Manor

Interface

Interface forum

DP83867E: DP83867E