Our problem:
We need to interface a TI advanced retimer (DS110DF111) to an Altera FPGA (Cyclone 10GX) for the purpose of exchanging high-speed serial data (10Gbps).
The retimer is powered from 3.3V, but internally there is a power supply for 2.5V (one question is related to this detail). The FPGA has the transceivers logic powered internally from 1.03V, but the high-speed transceiver itself is powered from 1.8V.
From the attached “AC Coupling …” pdf (SCAA059C), we can notice in Fig. 13 on page 8 that the direction LVDS driver-to-CML receiver (i.e., Altera FPGA to TI retimer) is pretty straightforward – we plan to install the 0.1uF AC-coupling caps close to the receiver, and we already have the 100ohm differential resistance part of the retimer package. There is some wording on page 8 about the self-biased state of the CML receiver in connection with the two 10K resistors in Fig. 13. Can you please elaborate a little bit about that? I don’t think we need those two 10K.
From the “Interfacing between … ” pdf file (SLLA120 - Fig. 13 on page 14), we can analyze the other direction CML driver-to-LVDS receiver (i.e., TI retimer to Altera FPGA). Again, the AC-coupling caps were already in our design, but we have few additional questions:
1.One question is about the pull-ups on the CML driver. What is the VDD voltage in that picture? Is it 2.5V because of the retimer’s internal supply? or 3.3V? The retimer spec sheet gives only the differential output voltage. According to the spec, we cannot use the VDD=2.5V pins (in 3.3V mode) for these pull-ups, right?
2.Next question is about the “termination” resistors on the receiver’s side (LVDS) … we have a differential termination inside the FPGA, much like the retimer has (not shown in this pic) … so, do we still need the external Z0 resistors (50 ohm) connected to the receiver common mode voltage? … if yes, can we use 1.8V if in fact this value is 1.25V for LVDS? … we don’t have a 1.25V supply … The third attached paper (also a TI doc – SNLA180) says that there might be a +/-1V common-mode range around the 1.25V (for LVDS). Is that correct for all LVDS manufacturers, including Altera? … if yes, does that mean that we can really make VTERM=1.8V? … we would still have to check with Altera, to find out their tolerance for this issue.
We would be grateful to you for an answer to your earliest convenience.
Thank you.
