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SN65DSI83-Q1: Gating LVDS output

Part Number: SN65DSI83-Q1

To whom it may concern,

We require the LVDS outputs to be Hi-Z during the initialisation of the MIPI bridge.

From the datasheet it seems the only way to make the LVDS Hi-Z is as follows:

- De-assert the EN signal

-> This prevents the I2C commands from acknowledging when configuring the CSR at initialisation

- Entering ULPS

-> This is entered by transitioning the input MIPI signals to LP00 state, which is contrary to the required LP11 state when initialising

Please  confirm if there is alternative way or workaround that allows to make LVDS Hi-Z during initialisation.

Many Thanks,

Bhav

  • Hi Bhav,

    Unfortunately I don't believe there are any other alternative methods to make the LVDS Hi-Z. Why is this a requirement for your application? During conditions when no video data is passing from the DSI input to the LVDS output, the DSI83 will just transmit zero value pixel data on the LVDS outputs.

    Regards,
    I.K.
  • We have timing requirements when powering up our display wrt valid data being present.  

    We see that when the EN is asserted, the common voltage is present on the LVDS outputs which is back powering the display’s driver IC though its protection diodes.

    Ideally, we would want the LVDS outputs to remain Hi-Z until we have configured MIPI bridge to produce valid data.

    Our display does not support warm reset and must be powered down when valid data is not present.