Hello,
i have questions regarding the output impedance control setting of the GBit PHY DP83867.
The output impedance can be configured with Bit 4:0 in the I/O Configuration Register (IO_MUX_CFG) with address 0x0170.
In the newest datasheet the discription of these bits is: "Output impedance approximate range from 35-70 Ohm in 32 steps. Lowest being 11111 and highest being 00000. Range and Step size will vary with process. Default is set to 50 Ohm by trim. But the Default Register value can vary by process. Non Default values of MAC I/O impedance can be used based on trace impedance. Mismatch between device and trace impedance can cause voltage overshoot and undershoot."
If i understand this correctly a config of 11111 always results in an output impedance of 35 Ohm. What is the tolerance of this 35 Ohm over all produced parts in the future? Is the tolerance higher than 3 Ohm?
Are there any experiences or production-statistics to estimate the variation of the output impedance of DP83867 for a fixed configuration of these bits?
Background Information:
At a new product all DP83867 on prototypes seem to have a default setting of 01101 (Bit 4:0 of 0x0170). This should represent 50 Ohm output impedance for this production date.
But we get the best signal integrity on our PCB with config 10010 cause of the production tolerance 50 Ohm +/-10% for trace impedance of our PCB manufacturer (approximately 47 Ohm at the prototypes).
For future production we don't expect the impedance of the PCB traces (47 Ohm) to vary because the PCB manufacturer has to use the same materials and processes. But we can't estimate the variation of the output impedance of DP83867 with register config 10010 with the actual datasheet.
So we try to figure out the best of the following possibilities for series production:
1) Always config the Bits 4:0 of register 0x0170 with 10010 over MDIO communication. --> 47 Ohm output impedance on prototypes but we don't know how much this can vary at future parts.
2) Always config the Bits 4:0 of register 0x0170 with 11111 over MDIO communication and place 12 Ohm external series resistors at every output pin of the PHY. -> 35 Ohm (+/- tolerance) + external 12 Ohm
3) Leave the default values for trimmed 50 Ohm. So the signal integrity is not the best but it is always the same for all production cases. -> 50 Ohm with small tolerance but no perfect match with 47 Ohm PCB trace.
