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DP83867IR: DP83867IR, RGMII, how to connect the clock to GTX_CLK to handle both 1000M and 100M?

Iven Xu
Intellectual 2090 points
Part Number: DP83867IR


Hello,

Here is a question, I want to use RGMII of DP83867IR to handle both 1000M and 100M mode.

you can see below figure(from datasheet), in RGMII configuration, the clock coming from MAC to PHY(GTX_CLK) is 125M , and the RX_CLK can be configured by the register 0x0170 to output the 25M or 125M for MAC. 

but how to configure the GTX_CLK to handle both 1000M and 100M mode, because it is 125M DDR clock in 1000M RGMII mode, but how to handle 100M RGMII mode? thanks.

Best Regards

Iven Xu

  • 0
    TI__Mastermind 26320 points
    Hi Iven,


    GTX_CLK clock adapts to link rate negotiated on the MDI side. If link is negotiated for 1000M, it provide 125MHz, if link is negotiated for 100M, it reduces the clock speed to 25MHz.


    Hope it clarifies.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Intellectual 2090 points

    HI Geet,

    thanks for your response.

    1, so your mean, the GTX_CLK can auto adapts to link rate either 1000M or 100M. just want to double confirm:

    the GTX_CLK basically is coming from the MAC, so the MAC output clock should be always 125M, then GTX_CLK of the DP83867IR can auto adapts the clock to 125M for 1000M link rate or 25M for 100M link rate, right?

    2, How about the RX_CLK, does customer have to configurate the 0X0170 for 125M for 1000M or 25M for 100M? or the PHY can auto adapts the output clock?

    Best Regards

    Iven Xu

  • 0 in reply to Iven Xu
    TI__Mastermind 26320 points
    Sorry, I mixed MII and RGMII interface.

    What I meant is that RX_CLK ( clock out from Phy) will adapt the Link rate on the MDI side to 125 or 25M. Based on the this MAC shall also adapt the GTX_CLK to 125 or 25M.


    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Intellectual 2090 points

    Hi Geet,

    I am confused and can not full understand your short response.

    could you please help explain more details? thanks.

    1, customer used the RGMII to support both 1000M and 100M mode.

    what shell customer to do in schematic design of GTX_CLK and RX_CLK? back to my previous question and the datasheet screenshot about RGMII.

    thanks and best regards

    Iven Xu

  • 0 in reply to Iven Xu
    TI__Mastermind 26320 points
    Hi Iven,

    No special handling is needed on RX_CLK and GTX_CLK to switch between 1000M and 100M mode. Based on the Link speed negotiated with Link Partner, Phy adjusts the frequency on RX_CLK and communicates the link speed negotiated to MAC using inband signalling. Based on the inband signalling information, MAC shall adjust the GTX_CLK frequency as well.

    Please refer section 5 in below link for more details on RGMII interface specifications.

    wenku.baidu.com/.../d3d6c6d63186bceb19e8bb11.html


    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Mastermind 26320 points
    Hi,

    I am closing this thread. Incase you still have issues, kindly open new thread and give reference to this thread.

    Regards,
    Geet