DS90UB933-Q1: What PCLK input jitter, max = 0.45UI means?

Part Number: DS90UB933-Q1

Hi Team,

Customer wants to know the meaning of PCLK spec, input jitter.

Is this for PCLK pin (input pin of 933)?, so if the PCLK including a lot of jitter over 0.45UI, the lock status will be unlocked?

over 7 years ago

0 Davor Glisic over 7 years ago

TI__Expert 8165 points

Hello-

Yes, the maximum allowable jitter on the PCLK signal (that is applied to the 933 PCLK pin) is 0.45 UI. If the jitter is higher than that, the operation of the FPD-Link III Serializer-Deserializer pair would be unreliable and the Deserializer may lose lock.

Regards,
Davor

0 NY over 7 years ago in reply to Davor Glisic

TI__Expert 3040 points

Hi Davor, thank you very much for your answer. I understand. regards, ny

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DS90UB933-Q1: What PCLK input jitter, max = 0.45UI means?