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DP83867CR: MDIO access

na na78
Guru 16770 points
Part Number: DP83867CR

Hi

The customer says that PHY address and other data could not be read by MDIO.

RESET is released.

What should we check in the design first?

Could you please give us comment?

BestRegards

  • 0
    TI__Mastermind 26320 points
    1. Has customer tried reading all phy address from 0 to 31 ?
    2. If Phy is out of reset, you shall see clock on RX_CLK ( 2.5MHz)

    What is the interface used to read the MDIO ?

    Regards,
    Geet
  • 0 in reply to Geet Modi
    Guru 16770 points
    Hi Geet

    Thank you for your reply.

    PHY MDC/MDIO has interface with FPGA.

    When they confirmed the initialization of FPGA, the trouble has been solved.
    But another issue has come up.

    RX_CLK is not observed.

    I will re-check strap pins if they are in range with target voltage.

    Let me update if the issue has not solved.

    BestRegards