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DS90UB947-Q1: Dual Lane Pixel Clock

Jared Becker
Genius 11845 points
Part Number: DS90UB947-Q1

Hi Team,

I am trying to determine the proper PCLK setting when using the 947 in dual lane mode. The display I am driving has the following specs:

H width: 1920

H Blanking: 160

V Height: 1200

V Blanking: 16

Refresh Rate: 60fps

Using those specs, I calculate a PCLK of 151.76MHz. But since I am using dual lane, do I halve the PCLK to 75.88MHz?

The datasheet is unclear in the dual lane most section.. "... with each FPD-Link III TX port running at one-half the frequency"

Does this mean I need to halve the frequency? Or does the part do that on its own and I should feed it 151.76MHz?

Thank you in advance for the support,

Jared

  • 0
    TI__Expert 8165 points
    Hello Jared,

    You need to feed it 151.76 MHz. In Dual Link Mode, each FPD-Link III would run at PCLK/2.

    Regards,
    Davor
  • 0 in reply to Davor Glisic
    TI__Genius 11845 points

    Hi Davor,

    Thank you for the clarification. So the 947 changes the clock speed from 151.76MHz at the input to 75.88MHz on each FPD-Link, correct? 

    What happens once the links are deserialized by the 948.. does the clock output go back to 151.76MHz?

    Thank you for the support.

    Jared

  • 0 in reply to Jared Becker
    TI__Genius 11845 points

    Hi Davor,

    Have you had a chance to investigate my question above? Thanks

    -Jared

  • 0 in reply to Jared Becker
    TI__Expert 8165 points
    Hi Jared,

    Sorry for the delay. Yes, the output pixel clock (PCLK) would be 151.76 MHz. Depending on how the 948 is configured, the oLDI clock would either match the PCLK (single oLDI ouput) or remain split at PCLK/2 (dual oLDI outputs). See Figure 31 (Datapath Configurations) in the UB948 datasheet.

    Regards,
    Davor
  • 0 in reply to Davor Glisic
    TI__Genius 11845 points

    Hi Davor,

    I am seeking clarification again with regard to PCLK input frequency into the 947. I reviewed another E2E post, which looks like a similar issue to what I was asking about: 

    Here is the final post in that thread:

    for both single OpenLDI or dual OpenLDI port, the total pixel clock is 170MHz. for dual, the real input lVDS clock is 85MHz. for single OpenLDI port, the real input maximum LVDS clock is 170MHz.
    In your application, to support 1920x720, the LVDS clock should be ~90MHz or lower.

    When the person refers to "total pixel clock is 170MHz", are they referring to the clock that is feeding the 947?

    When the person refers to "real input lVDS clock is 85MHz" for dual link, are they referring to the clock frequency in the link (between the 947 and 948)?

    When the person refers to "real input maximum LVDS clock is 170MHz" for single link, are they again referring to the clock frequency in the link (between the 947 and 948)?

    If everything above is correct, what is meant by the last statement "to support 1920x720, the LVDS clock should be ~90MHz or lower." Was this intended for only single link only? 

    Here is what I'm ultimately trying to understand (which is similar to the other post)..

    1. In single link mode (when there is only one physical cable between the 947 and 948), is the maximum clock frequency that I can feed the 947 from the SoC limited to 90MHz as the front of the datasheet says (page 1), or 170MHz as the electrical specs state on page 6?

    Essentially, can i drive the display that I mentioned above with a single link (single cable between 947 and 948) at 152MHz?

    Thank you,

    Jared

  • 0 in reply to Jared Becker
    TI__Expert 8165 points

    Hello Jared,

    Below  is a table that summarizes the relationship between PCLK, OLDI input clock, and FPD3 clock for each possible permutation of OLDI input and FPD3 output modes for the 947.  This should answer all your questions.

    Let me know if further clarification is needed.

    Regards,

    Davor

    OLDI Input Mode OLDI Input CLock Equivalent PCLK FPD3 Output Mode FPD3 Port 0 Clock FPD3 Port1 Clock
    Dual OLDI Input 12.5 MHz - 48 MHz 25 MHz - 96 PCLK Single FPD3 Output 25 MHz to 96 MHz N/A
    Dual OLDI Input 25 MHz - 85 MHz 50 MHz - 170 MHz Dual FPD3 Output 25 MHz to 85 MHz 25 MHz to 85 MHz
    Single OLDI Input 25 MHz - 96 MHz 25 MHz - 96 MHz Single FPD3 Output 25 MHz - 96 MHz N/A
    Single OLDI Input 25 MHz - 170 MHz 25 MHz - 170 MHz Dual FPD3 Output 25 MHz to 85 MHz 25 MHz to 85 MHz