Linux/DS90UH927Q-Q1: Receiver ds90ur910 can not recognise clock/data transfered

John Zhao

Part Number: DS90UH927Q-Q1

Tool/software: Linux

Hi All；

I am developing ds90ub927q transmit four LVDS data an one LVDS clock signals to ds90ur910 on i.Mx6 . Now I meet a problem that Receiver ds90ur910 can not recognise clock/data transfered . The receiver 910 was verified on other project.

927 Schematic as follow:

The default registers on 927 is not configured.We set BKWD pin and MAPSEL pin low ,Trasmit signals Is 4 LVDS（JEIDA mode） 1024*600*51.2(Mhz). We use the oscilloscope to measure the FPD link signal of the 910 receiver ，It is 1.4GH and the Eye diagram shows good signal quality。But 910 can not recognise singal inputs.

THen I set the 927 to BIST mode Refer to AN-2198 documentation as follows:

ds90ub927_write_reg(0x65, 0x02);

ds90ub927_write_reg(0x64, 0x00);

ds90ub927_write_reg(0x66, 0x03);

ds90ub927_write_reg(0x67, 0x06); //set pclk 33.3Mhz

ds90ub927_write_reg(0x66, 0x07);

ds90ub927_write_reg(0x67, 0x20);

ds90ub927_write_reg(0x66, 0x08);

ds90ub927_write_reg(0x67, 0x03);

ds90ub927_write_reg(0x66, 0x09);

ds90ub927_write_reg(0x67, 0x1E); // set hactive*vactive 800*480

ds90ub927_write_reg(0x66, 0x04);

ds90ub927_write_reg(0x67, 0x98);

ds90ub927_write_reg(0x66, 0x05);

ds90ub927_write_reg(0x67, 0xD4);

ds90ub927_write_reg(0x66, 0x06);

ds90ub927_write_reg(0x67, 0x20); //set h total framsize 1176 v total frame size 525

ds90ub927_write_reg(0x66, 0x0C);

ds90ub927_write_reg(0x67, 0xD8);

ds90ub927_write_reg(0x66, 0x08);

ds90ub927_write_reg(0x67, 0x23); //set h back porch 215 v back porch 35

ds90ub927_write_reg(0x65, 0x03);

ds90ub927_write_reg(0x64, 0xD1)//Enable Pattern Generation

But receiver 910 still can't identify the input signals .

Can anyone help me?

Thanks

over 7 years ago

0 John Zhao over 7 years ago

Prodigy 85 points

Sorry ,the BKWD pin is high.

0 Steven(Shenzhen) Shi over 7 years ago in reply to John Zhao

TI__Mastermind 30515 points

You means the back compatibility with ur910 is enabled?
what is the lock status of ur910?

regards
Steven

0 John Zhao over 7 years ago in reply to Steven(Shenzhen) Shi

Prodigy 85 points

Hi Steven:

Thanks for your reply.

As long as the FPD Link Line is connected to the UR910 , LOCK pinit will be pulled high. Even if I turn off the output of 927, the LOCK PIN is still high.

Now I have a 927 board that someone else uses MCU to do, but i can't find out its register's settings . After connecting with UR910, the UR910 side can display the test picture (color switching test mode), but there will be problems with our bottom board, the PIN of the current stage 927 The status is the same as the MCU board, but UR910 still can't parse the data I sent. So I suspect that the configuration of the test mode register on my side may be problematic.

Check the manual of the UR910. The UR910 will check clock and resolution of input signals, as shown below. But I configured 800*480*33MHz for the output of the 927 as he requested. The UR910 end system still prompted that the data could not be parsed.

Is it related to the input signal? According to your experience, you can see where there is a problem.

0 Steven(Shenzhen) Shi over 7 years ago in reply to John Zhao

TI__Mastermind 30515 points

1. what is the pin "BKWD" setting of UB927? BKWD=1 is required to connect with UR910.

2. HSYN, vsync's high or low availability? (setting 0x11 to make it compatible with input video).

regards,

Steven

0 John Zhao over 7 years ago in reply to Steven(Shenzhen) Shi

Prodigy 85 points

HI Steven:
BKWD pin of 927 is high now.
Do you mean set UR910's 0x11 register to compatible with input video that outputs of 927 (Across test settings )?

0 John Zhao over 7 years ago in reply to Steven(Shenzhen) Shi

Prodigy 85 points

0x11 of UR910 is 0x80 now, UR910 can show test pictures(color switching) with an other MCU 927 boards.

0 Steven(Shenzhen) Shi over 7 years ago in reply to John Zhao

TI__Mastermind 30515 points

pls check the video format in your board. if not confirmed, you can try diff. setting for it?
also, you can use CSI external timing for test based on your video format. If possible, you can measure the UR910's CSI2 output signal, is it correct?

regards,
Steven

0 John Zhao over 7 years ago in reply to Steven(Shenzhen) Shi

Prodigy 85 points

For 927 test mode settings:
ds90ub927_write_reg(0x65, 0x03);
ds90ub927_write_reg(0x64, 0x11)//Enable Pattern Generation
0x65 is 0x03, bit4 is 0(0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness. (default)).MCU board settings was lost, Can't find it.
In UR910 side, log shows that can't dequeue input signals, So i Can't measure UR910's outputs.
MCU test board outputs 24-bit video signals