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DS32EL0124: DS32EL0124 reading a register issue

Lin Hsian
Expert 1580 points
Part Number: DS32EL0124

Hi, 

Our customer used DS32EL0124 for FPGA high speed data transmission but when he try to follow  DS32EL0124 DS page17 "reading a register issue description" to programming their FPGA code but  slave can't reply corresponding register while he write.

The DS of reading a register issue description as below:

1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drives a START condition. 7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 8. The Device drives an ACK bit “0”. 9. The Device drives the 8-bit data value (register contents). 10. The Host drives a NACK bit “1”indicating end of the READ transfer. 11. The Host drives a STOP condition. 12. The Host de-selects the device by driving its SMBus CS signal Low

Could you please share the DS32EL0124 SMBus clock waveform which follow the description as above.

And customer can follow the waveform to programming  their FPGA code to generate right communication data clock.

Thank you.

Warm Regards,

Kevin Lin

  • 0
    TI__Guru 64326 points

    Lin,

    All values timing values and voltage levels for SMBus are located in datasheet on (pg. 6). Please see image below or waveform and corresponding timing parameters from datasheet. 

  • 0 in reply to Malik Barton57
    Expert 1580 points
    Hi,

    Customer encounter issue is FPGA(Mater)/DS32EL0124(Slave) communication issue and need follow DS32EL0124 DS page17 “reading a register” step1~12 to set.
    And the question point is step4: The Host drives the 8-bit Register Address(FPGA) and step5: The Device drives an ACK bit (“0”) from DS32EL0124 but description didn’t mention the timing setting.

    Simply said, if we can provide step1~ step12 description to waveform(even drawing by hand) for Kuo-Wei bench mark as well.

    www.ti.com/.../ds32el0124.pdf

    Ps1. Altera has SMBus IP but can’t communication with DS32EL0124.
    Ps2. Customer tried to coding SMBus waveform depend on DS page9 Figure 3 which same as Altera SMBus IP waveform.
    Ps3. Also, double confirm the VIH/VIL are meet SMBus DS spec.

    Warm Regards,
    Lin
  • 0 in reply to Lin Hsian
    TI__Guru 64326 points

    Lin,

    I will work to provide the waveform on this thread, unfortunately we do not have these on hand and the waveform will need to be generated. In the meantime, could you answer the following questions:

    • Can you write to DS32EL0124? If so, are you seeing ACK commands sent by slave?
    • What slave address are you using to access DS32EL0124? Should be the 7 bit address corresponding to B0'h

    The ACK sent by the slave device should be seen by the master every 9th clock cycle indicating a byte, sent by SMbus master, was received (timing for step 5). SMBus master should not be controlling the data line at this time.

    Also in step 4 (as referenced below, see green highlight) the register address should be the desired DS32EL0124 register address.

  • 0 in reply to Malik Barton57
    TI__Guru 64326 points
    Lin,

    Is any more support needed for this issue? If so please reply with any relevant details so that I can further assist you. For now I will be marking this thread as "TI Thinks Resolved". If this issue is resolved could you please share the resolution to this issue with the forum.
  • 0 in reply to Malik Barton57
    Expert 1580 points
    Hi Barton, your solution work from customer side and no problem now. Thank you.
  • 0 in reply to Lin Hsian
    TI__Guru 64326 points
    Lin,

    Could you clarify which suggestion worked for you? I would like to have the answer publicly available for others that might run into this issue.
  • 0 in reply to Malik Barton57
    Expert 1580 points
    Hi,
    Master need wait slave Ack signal low then high(half clock period ) and master can start transmit data to slave.

    Warm Regards,
    Lin