Hello Team,
the SN65HVD10x has a driver enable delay that is specified by max. 5us.
We do see that the majority of the device actually have a delay more in the range of 1us but there are very few that are in the range of 3us.
From statistical perspective I would say that the number of devices that will have 5us delay would be less than the typical ones (even if is not specified in datasheet).
There are some IOLink applications where the message must be sent back within 3.5us and with 3us delay the first bit could be cut out, generating errors.
- What is influencing the delay of the buffer? (within the 1-5us range)
- Is it only process variation and temperature or are there other parameters that let it change?
V L+ is also influencing the delay, what does it change internally that let the delay being influenced by L+.
The internal current generators are not referring to internal ref, but to L+
Thanks,
SunSet