Hi Team,
I'm understanding DP83867 can support Jumbo packets without any register changes.
but I think it should need more accurate clock sync to avoid FIFO overflow and underflow on Phy and Mac.
Fundamentally, IEEE802.3 defines +/-100ppm clock tolerance for ref clock in a system. But this requirement only allows up to 1518byte packet communication with max IFG(Inter frame gap). In order to deal with Jumbo packet such as 9k byte, more accurate clock source should be required.
Could you tell me the following points to design safety system?
1. How much accurate clock does it need for 9k packets transmission safely?
2. Are there any figures showing internal clock architecture of DP83867?
3. Which clock should be used as system ref clock? Or, is separated clock architecture acceptable(Using different clock sources on Mac and Phy)?
Regards,
Takashi Onawa