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DS90UB960-Q1: signal integrity questions

Alberto Doronzo
Expert 4991 points
Part Number: DS90UB960-Q1


Hi,

I have a customer working with the x960 and he is asking the following questions:

  1.  is there a scrambling polynomial or 1B or 2B for FPD-Link
  2. what is the speed of back channel for FPD-Lin
  3. what is the maximal length for a FPD-link cable (single-ended and differential
    1. what is the max speed at the length?
    2. is there a chart?
  4. how is the equalizer signal verified from the input to the output

Thank you!

Regards,

Alberto

  • 0
    TI__Genius 10475 points
    Alberto,
    1. The FPD-Link uses scrambler/de-scrambler , and it is LFSR-based polynomial.
    2. The max backchannel speed can vary based on the mode, for the default synchronous mode the rate is 50 Mbps. Refer to 960 datasheet AC electrical characteristics table 6-6 for fBC.
    3. For the max PCB return/insertion loss and other PCB characteristics refer to the 960 datasheet table 264.
    4. Not sure if I follow thee question, for equalizer details refer to the datasheet. The CMLOUT can be used to monitor the recovered input of the deserializer signal after the EQ stage.
  • 0 in reply to Palaniappan Manickam
    TI__Expert 4991 points

    Hi Palaniappan,

    thanks for your response.

    Regarding question#4 :

    How is this set up: i.e. does the receive measure the eye opening and sends a command thought the back-channel to the serializer to change the gain / delays/ slew?

    Or is there an internal feedback at the serializer to adjust the parameters?

    Thank you!

    Regards,

    Alberto

  • 0 in reply to Alberto Doronzo
    TI__Genius 10475 points
    Alberto,
    Please refer to the 960 datasheet starting from section 7.4.7.3 foe adaptive equalizer algorithm. It basically steps through the equalizer settings and finds the optimal value that allows the CDR to maintain proper lock. The AEQ status and configuration settings are selected through registers 0xD2 to 0xD5.