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SN75DPHY440SS: Operation a frequencies below 100Mhz

Harry Der
Intellectual 270 points
Part Number: SN75DPHY440SS

The MIPI CSI2 specification for the HS clock is 80 to 750Mhz.  What happens to this part do if the MIPI clock frequency is between 80 and 99.9999999Mhz?

  • 0
    TI__Guru**** 176811 points
    Harry

    SN75DPHY440SS DACP minimum frequency is 450MHz, so it will not support 100MHz input frequency.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 270 points
    Hi David, First page of the datasheet for the part reads CSI-2/DSI Clock Rates From 100Mhz to 750Mhz. I just need to understand what happens below 100Mhz down to 80Mhz. Does the part not pass through the signals?
    Harry
  • 0 in reply to Harry Der
    TI__Guru**** 176811 points
    Harry

    The design is spec'ed to work down to 40MHz, but we tested the device and spec'ed the datasheet to be min of 100MHz for margin. Device functionality below 100MHz is not guaranteed.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 270 points
    Hi David, On the first page of the datasheet is the note "MIPI DPHY 1.1 Specification Compliant". The MIPI DPHY 1.1 specification states a bit rate of 80 to 1500Mbps or a clock rate of 40 to 750Mhz. How can this part be 1.1 compliant and only work down to 100Mhz which implies a 200Mbps data rate? I am not looking do go down to 40Mhz just down to 80Mhz.
  • 0 in reply to Harry Der
    Intellectual 270 points
    Opps I misspoke I really need it to go down to an 80Mbps data rate and a 40Mhz clock as you originally specified.

    Harry
  • 0 in reply to Harry Der
    TI__Guru**** 176811 points
    Henry

    The 80Mbps-1500Mbps bit rate range is being defined by the MIPI spec as a proposed solution, the actual data rate is being defined by the clock rate, which is being defined in table 26 of the MIPI spec: clock signal specification. In the clock signal specification, only max period is defined which is 12.5ns, corresponding to 80Mbps/40MHz. 100MHz still falls within the spec.

    The SN75DPHY440 will work at 40MHz as part of the design spec, but we spec'ed at 100MHz for margin.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 270 points

    Hi David,

    Thanks for the explanation on the DPHY specification.  I was referring to the last paragraph of section 4.1 of the specification that reads "a bit range of 80 to 1500Mbps per Lane.".  Maybe the SN75DPHY440SS part does not able to do de-skewing of the data lanes below 100Mhz.  I would like to know what the part does below 100Mhz as it may still be applicable in the application I have as de-skew below the 100Mhz or 200Mbps is probably not necessary given the width of  the eye pattern on the data relative to the clock.

    Harry

  • 0 in reply to Harry Der
    TI__Guru**** 176811 points
    Harry

    The SN75DPHY440SS will deskew from 40MHz to 750MHz. But the part has only been characterized, tested at 100MHz, I can't guarantee the device behavior below 100MHz since it is being not tested.

    Thanks
    David