TCA6424: FET which connects SDA line

Hello Hirotaka-san,

Just a heads up, the TCA64234 is Not Recommended for New Design. We recommend the A version: TCA6424A.

"What is FET which connects SDA line used for on Figure 18. Positive Logic?"
-(Yes), The FET is an NFET which would require a positive voltage on the gate to pull the signal to ground. It is controlled by the state machine of the device.

"Is there possibility that this FET keeps high level by latch up?"
-In normal operation, this should not happen. I can think of two cases where this could occur.
[1] if the device was in the middle of a transaction where it was controlling the data line but misses the clock pulses (sees 8 pulses but the master gave 9) so the state machine continues to hold the line until it sees the last clock pulse.
[2] if the device did not start up properly so the state machine is in a unknown state which could potentially hold the SDA line low.

In this kind of situation I would recommend send either 9 or 18 clock pulses on the SCL line. This is a procedure that should reset the state machine of the device and release the SDA line. It is also discussed in the I2C standard.

"In relation <Question2>, if this FET keeps high level, using rest input, does this FET returns to normal condtion?"
Yes, the reset pin will reset the state machine of the device and release the bus.

Thanks,
-Bobby