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Original question:

SN65HVD235: CAN Sampling and Sync

SN65HVD235: CAN Passive Error Flag

Henrique T.
Intellectual 490 points
Part Number: SN65HVD235


I didnt understand very well those statements:

"After transmission of an error frame, an error passive node must wait for 6 consecutive recessive bits on the bus before attempting to rejoin bus communications" (Microchip)

"Therefore, error-passive receivers shall always wait for six subsequent equal bits after detecting an error condition, until they have completed their error flag" (ISO 11898-1)

"The error passive station waits for six consecutive bits of equal polarity, beginning at the start of the passive error flag. The passive error flag is complete when these 6 equal bits have been detected" (CAN 2.0 Specification)

Could someone explain me that?

They're all telling about the same thing?

  • 0
    TI__Guru 74322 points
    Henrique,

    Yes, all three of these are the same specification for a CAN controller. When CAN controllers detect CAN errors, they will send an Active error frame which disrupts communication on the bus, and causes all nodes to increment their error counter. Once a certain value is reached in the error counter, the node will go into error passive mode (this value is typically 127, but that is not always the case). When the node goes into error passive mode, it will continue to send error messages, but in a passive method, as 6 recessive bit, as to not disturb the bus communication. In this way, the transmitter of said error will continue the increment its own error counter.

    So this is just defining how the error passive state handles error flags once going into error passive mode. There is more explanation on this that I can go into, but for now, does this answer your question?

    Regards,
  • 0 in reply to Eric Hackett
    Intellectual 490 points
    I understood what you explained. But I'm still having difficulties about connecting those facts to the three statements I quoted.
    For example:

    "The error passive station waits for six consecutive bits of equal polarity, beginning at the start of the passive error flag. The passive error flag is complete when these 6 equal bits have been detected" (CAN 2.0 Specification)

    The passive error flag is 6 consecutive recessive bits.
    Ok, so the passive error node sends the passive flag when detecting an error condition. After finishing the transmission of the last bit (of 6) it waits the detection of six consecutive bits of equal polarity on the bus (send by who??) to complete the error flag and only after that, it sends the error delimiter (8 recessive bits) ?
  • 0 in reply to Henrique T.
    TI__Guru 74322 points
    Henrique,

    Because the passive error flag is recessive, it will not interrupt communication on the bus. If the transmitter is in the passive error state, detecting its passive error flag will be immediate, because it is the only node communicating and thus nothing will interrupt the 6 recessive bits being sent by itself. However, if a receiver is in the error passive state and detects an error, it will send out its passive error flag but can be interrupted by dominant bits sent by other nodes. The receiver will continue to send the passive error until it detects six recessive bits in a row, and it will then know that the passive error flag was sent correctly.

    Does that make sense? This is a somewhat complicated topic, so please feel free to ask any questions or for clarification.

    Regards,