XIO2001: GRST input glitch during initial power-up

Oba,

If I understand your description and figure correctly this glitch may cause issues as VDD for XIO2001 is not stable at the appropriate voltage level for a correct power-up.

VDD should be stable before GRST is pulled high by reset IC. I would confirm that when using your reset IC 1.5V and 3.3v rails (including PCIR) are all pulled to appropriate voltage levels and stable before GRST goes high.

Hello,

 

Thanks. Can I explain my question again to avoid miscommunication.

The below figure is the image what I want to ask.

GRST could be a kind of HIGH until power rails reaches at about 0.8V because reset ICs generally can’t pull low till about 0.8V(V_POR).

 

Could this glitch really cause any problem?

The voltage is very low when the glitch output. Can internal circuit start to run with this kind of low voltage?

Also after this short glitch, GRST is pulled low. I feel that resets the device again. So I feel this level of glitch is not problem.

 

Regards,

Oba

Oba,

I believe you are correct, this glitch should not be a issue as long as it stays below the VIL limit in section 6.10 3.3-V I/O Electrical Characteristics of datasheet and is not a sustained pulse, goes back low. 

Hello,

Regarding VIL limit you mentioned,  that is also one my question.
The problem is this value, VIL_MAX is defined as "0.3 * VDD_33". It is not fixed value.
So during initial power-up and having GRST glitch, GRST is almost the same as VDD_33 although VDD_33 is less than 0.8V.
When VDD_33 = 0.8V, VIL_MAX = 0.8V * 0.3 = 0.24V.
So during this glitch, VIL_MAX is NOT kept for GRST. But I feel it doesn't make sense because VDD_33 is low voltage.
How to think about this?

Regards,
Satoshi Obata

Oba,

Even when VDD_33 is low this glitch could cause issues taking XIO2001 into a unstable state (internal circuits may try to turn on when there is not an appropriate voltage level on VDD_33). However since the pulse is small you may not see any issues on XIO2001. Adding a small capacitor may help mitigate this issue. Could I see a schematic of the reset line for this application for more details?

Hello Malik,

The schematic is not still available because of waiting for this answer.

So even if VDD_33 is low voltage during GRST glitch, we can’t remove the possibility to cause some issues during this period because the device could be in unstable state.
But because the glitch period is short and the voltage is low, it probably doesn’t cause any issue. And also after the glitch, GRST is asserted again. So after that, the device should work correctly.

Does that make sense?

What kind of problems could occur during glitch?

Regards,
Obata

Obata,

This makes sense and I am unsure of what issues may occur other than the device try to do internal initialization and being interrupted causing the unstable state I mentioned before. Would it be possible to ramp the reset IC power rail before the XIO2001 3.3 V rail?