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TFP401A: Data Setup and Hold Times

Part Number: TFP401A

Dear, Support Team.

I have a question about TFP 401A data sheet on page 9 "Figure 4. Data Setup and Hold Times to Rising and Falling Edges of ODCK".
When 1 pixel per clock, the setup time is 0.6 nsec before ODCK and the hold time is 1.8 nsec after ODCK?
I am looking for details of timing chart and application notes by replacing from Lattice SiI 1161.

Best Regards,
Hiroaki Yuyama