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DS250DF410: DS250DF410

Part Number: DS250DF410


Hi Ti:

We are used DS250DF410 for backplane Reach Extension. and operating the device at 20.6Gbps data rate.

signal path: Switch_1 ->BP->DS250DF410->Switch_2;  Switch_1 Tx pre-cursor of 2dB,post-cursor of 0dB.

Using SigconArchitect  Adjusted, Eye Opening Monitor ,HEO>0.5 and VEO > 360mV.

But it still have some bits errors,at long time Test(24h).

How do we adjust next?

  • Hi,

    Did you try enabling the DS250DF410 PRBS checker to confirm that errors are occurring at the retimer input? You should do this to isolate whether the link segment with issue is "Switch Tx to Retimer Rx" or "Retimer Tx to Switch Rx"

    Your reported HEO > 0.5UI and VEO > 360mV values both meet and exceed TI's recommended minimum thresholds for error free operation. The retimer eye opening values are however for high probability BER of 1E-6. If errors are indeed being observed by retimer PRBS checker, then we would be dealing with low probability jitter, either random jitter or bounded uncorrelated jitter from crosstalk. One thing you may try in such case is increasing the retimer CDR bandwidth by increasing the CDR charge pumps. A higher CDR bandwidth allows it to better track the input jitter. The default value for the DS250DF410 CDR charge pumps is 5. You may increase it to 9 or 10 and see if the long duration test bit errors go away.

    Table 1. Adjust CDR Bandwidth

    STEP

    SHARED/ CHANNEL REGISTER SET

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

    COMMENT

    1

    Channel

    Write

    1C

    0

    FC

    Force CP = 5

    0

    FC

    Force CP = 6

    0

    FC

    Force CP = 7

    24

    FC

    Force CP = 8

    24

    FC

    Force CP = 9

    24

    FC

    Force CP = 10

    24

    FC

    Force CP = 11

    24

    FC

    Force CP = 12

    24

    FC

    Force CP = 13

    24

    FC

    Force CP = 14

    24

    FC

    Force CP = 15

    48

    FC

    Force CP = 16

    Table 2. Adjust CDR Bandwidth (continued)

    STEP

    SHARED/ CHANNEL REGISTER SET

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

    COMMENT

    2

    Channel

    Write

    9E

    B4

    FC

    Force CP = 5

    D8

    FC

    Force CP = 6

    FC

    FC

    Force CP = 7

    0

    FC

    Force CP = 8

    24

    FC

    Force CP = 9

    48

    FC

    Force CP = 10

    6C

    FC

    Force CP = 11

    90

    FC

    Force CP = 12

    B4

    FC

    Force CP = 13

    D8

    FC

    Force CP = 14

    FC

    FC

    Force CP = 15

    0

    FC

    Force CP = 16

    3

    Channel

    Write

    9

    8

    8

    Enable charge pump override

    4

    Channel

    Write

    0A

    40

    40

    Enable cp_idac override

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer