I am trying to get an FPGA design in Xilinx K7 series device to talk to the DP83867IS in the design using RGMII. This has proven far more difficult than anticipated as I have been unable to get the RGMII link from MAC to PHY to pass data reliably. I decided to do some probing of the test hardware and came across something very odd: in RGMII at 1 Gbps, I see receive data on all four data lanes with the expected 125 MHz RX_CLK. If I switch to 100 Mbps (pulling plug from gigabit switch and inserting into 10/100 switch) I observe the clock switching down to 25 MHz. However, the receive data is a different matter: I'm only seeing data activity on RX_D2 while the other lanes stay constant, some high, some low. This is observed on an oscilloscope at the PHY package pin. I've read all the registers that confirm the pin-strap settings should be putting it in RGMII mode.
On the analog link, the link easily establishes the auto-negotiated speed and link status registers all look ok. At the RX_D2 line on the PHY, I think I can be sure that no fault in the FPGA design could be causing this, unless there were some pin-strap interplay with the FPGA boot / reconfiguration process. What could cause the PHY to only output on RX_D2 in 100 Mbps mode? It does share functionality with SGMII_SOP pin but that seems implausible as SGMII mode would produce a clock on RX_D0/SGMII_COP.
