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XIO2001: XIO2001

Imthiyaz Khan P M D
Prodigy 30 points
Part Number: XIO2001

We are using PCIE to PCI bus bridge in our single board computer Which is Intel based board.

We are using XIO2001 for PCIE to PCI interface. 

Manufacturer Part Number

    XIO2001IZGU

Description

    IC PCI-EXPRESS/BUS BRIDGE 169BGA

We have checked all the modern pci cards on this bridge and we are able to identify the pci cards and it is working in OS environment.

Our issue is, We have a card which is developed in 1990's. This is Network card. 

PCI card is connected on this bus and is requesting memory above MMIO space(4GB). Can you please tell us about its behavior?

Thanks,

Imthiyaz

  • 0
    Guru 316780 points
    "Above 4GB" would mean that that device is 64 bits. Is that actually the case?

    What exactly does that card report in its configuration registers?
  • 0 in reply to Clemens Ladisch
    Prodigy 30 points

    The card is 32-bit only. But it is requesting memory above 4GB.

    The PCI configuration space data is as below:

      PCI Segment 00 Bus 05 Device 00 Func 00 [EFI 0005000000]
  00000000: 00 00 01 00 00 00 80 4A-AA 3C C3 55 10 20 00 00  *.......J.<.U. ..*
  00000010: 08 00 00 00 08 00 00 00-00 00 00 00 00 00 00 00  *................*
  00000020: 00 00 00 00 00 00 00 00-00 00 00 00 FF FF FF 7F  *................*
  00000030: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
 
  00000040: 20 00 00 00 02 00 01 00-00 00 00 00 00 00 00 00  * ...............*
  00000050: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  00000060: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  00000070: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  00000080: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  00000090: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000A0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000B0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000C0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000D0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000E0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
  000000F0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00  *................*
 
Vendor ID(0): 0000                     Device ID(2): 0001
 
Command(4): 0000
  (00)I/O space access enabled:       0  (01)Memory space access enabled:    0
  (02)Behave as bus master:           0  (03)Monitor special cycle enabled:  0
  (04)Mem Write & Invalidate enabled: 0  (05)Palette snooping is enabled:    0
  (06)Assert PERR# when parity error: 0  (07)Do address/data stepping:       0
  (08)SERR# driver enabled:           0  (09)Fast back-to-back transact...:  0
 
Status(6): 4A80
  (04)New Capabilities linked list:   0  (05)66MHz Capable:                  0
  (07)Fast Back-to-Back Capable:      1  (08)Master Data Parity Error:       0
  (09)DEVSEL timing:             Medium  (11)Signaled Target Abort:          1
  (12)Received Target Abort:          0  (13)Received Master Abort:          0
  (14)Signaled System Error:          1  (15)Detected Parity Error:          0
 
Revision ID(8):     AA                 BIST(0F):  Incapable
Cache Line Size(C): 10                 Latency Timer(D): 20
Header Type(0E):    00, Single function, PCI device
Class: UNDEFINED - UNDEFINED - UNDEFINED
Base Address Registers(10):
     Start_Address  Type  Space    Prefetchable?     Size             Limit
  --------------------------------------------------------------------------
          00000000  Mem   32 bits  YES            80080000          8007FFFF
          00000000  Mem   32 bits  YES            80040000          8003FFFF
  --------------------------------------------------------------------------
Expansion ROM Disabled(30)
 
Cardbus CIS ptr(28):   00000000
Sub VendorID(2C):          FFFF      Subsystem ID(2E):      7FFF
Capabilities Ptr(34):        00
Interrupt Line(3C):          00      Interrupt Pin(3D):       00
Min_Gnt(3E):                 00      Max_Lat(3F):             00

  • 0 in reply to Imthiyaz Khan P M D
    Guru 316780 points

    As shown above, the base address registers are for the 32-bit memory space.

    Where exactly do you see an above-4 GB requirement? (The base address registers are not configured, and when they are configured, an address with the upper bits set to zero is a valid value.)

  • 0 in reply to Clemens Ladisch
    Prodigy 30 points
    Base Address Registers(10):
         Start_Address  Type  Space    Prefetchable?     Size             Limit
      --------------------------------------------------------------------------
              00000000  Mem   32 bits  YES            80080000          8007FFFF
              00000000  Mem   32 bits  YES            80040000          8003FFFF
      --------------------------------------------------------------------------
    As mentioned in above highlighted text, the size of individual BAR size is (2GB+512KB), (2GB+256KB) respectively. Thus the total size comes above 4GB.
  • 0 in reply to Imthiyaz Khan P M D
    Guru 316780 points

    From the PCI specification:

    The "Type" bits a zero in your case, so these are 32-bit address ranges. No address in the range can be above 4 GB; the addresses would just wrap around.

    Anyway, the size values shown cannot happen. Section 6.5.2.1 says:

    Power-up software can determine how much address space the device requires by writing a value of all 1's to the register and then reading the value back. The device will return 0's in all don't-care address bits, effectively specifying the address space required. Unimplemented Base Address registers are hardwired to zero.

    This design implies that all address spaces used are a power of two in size and are naturally aligned.

    And:

    Implementation Note:  Sizing a 32-bit Base Address Register Example

    Decode (I/O or memory) of a register is disabled via the command register before sizing a Base Address register. Software saves the original value of the Base Address register, writes 0FFFFFFFFh to the register, then reads it back. Size calculation can be done from the 32-bit value read by first clearing encoding information bits (bit 0 for I/O, bits 0-3 for memory), inverting all 32 bits (logical NOT), then incrementing by 1. The resultant 32-bit value is the memory/I/O range size decoded by the register.

    Apparently, that device does not implement the most significant bit of the base address register, i.e., it has a 31-bit bus. This hardware error breaks the above sizing algorithm. In any case, this has nothing do to with the XIO2001.