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TLK10232: Clock output is not coming from TLK10232CTR

Lakshmanan V
Intellectual 480 points
Part Number: TLK10232

Hi sir,

             I am using TLK10232CTR chip one of my project to convert XAUI to 10 GBASE- R mode.

  I am giving reference clock ( LVDS clock type ) 156.25Mhz to REFCLK[1:0]P/N pins of TLK10232CTR.

But there won't be any clock coming from CLKOUTAP/N & CLKOUTBP/N pins of TLK10232CTR.

by default how clock frequency should be come out from this chip?

we connected SFP+ module at 10 Gbase-R lane.

This SFP+ module is not deducting.

Please tell me steps to access this SFP+ module ( FTLX1475D3BTL ).

 I am attaching this schematic for your reference.

XAUI TO XFI USING TLK10232CTR SCHEMATIC .pdf

Regards

Lakshmanan V

  • 0
    TI__Guru 64326 points
    Lakshmanan V,

    We are looking into this issue and will get back to you as soon as possible.
  • 0
    TI__Guru 64326 points
    Lakshmanan V,

    CLOCK-OUT frequency will depend on your configuration of the registers below and implementation of TLK10232. By default CLOCK-OUT pins output the high speed side Channel A recovered byte clock (high speed line rate divided by 16 or 20). What are your configurations for these registers:

    0x1E.0x0002 Bit [6]: HS_VRANGE
    0x1E.0x000D Bit [6]: CLKOUT_DIV[3:0]
    0x1E.0x000D Bit [6]: CLKOUT_SEL[3:0]

    Below are some steps you can follow for getting a stable connection between TLK10232 and your SFP+ module.

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).
    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
    4. Disable link training by writing 16’h0000 to 0x01.0096
    5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.
    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.
    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

    Step 6 is a very important step in the process and you should monitor 0x1E.0x0010 for the error count. This allows you to measure your BER which should be minimized for a good link.