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DS90UB954-Q1: DS90UB954 Power Sequence Question.

Ian Wang
Mastermind 29700 points
Part Number: DS90UB954-Q1

Dear Sir,

Customer found sometimes it will occur CSI Error (0x4e bit3 is set) after power cycle initial UB953/UB954.

It will let host side cannot receive frame.

We checked UB953 spec. about power sequence, it need wait for "DEC LOCK TIME" between initial UB954 and initial UB953.

 

We checked with d/s for lock time(tDDLT), the max. will be 300ms 

Customer try implement lock time(tDDLT)=300mS found the issue will gone.    

But their end-customer has spec. for initial serdes duration need <=64ms.

Pls advise how we can do for satisfied no issue and duration<=64ms?

Thanks, Ian.

 

  • 0
    TI__Genius 10475 points
    Ian,
    The datasheet specs are what we can guarantee, so if the full AEQ range is used it would be a max of 300ms. If faster lock time is desired, it is possible to limit the AEQ range to achieve 30ms max for +/-3 AEQ settings, but the customer needs to test and qualify their system to ensure limiting the AEQ still gives sufficient performance to operate error-free based on their channel and system characteristics. Refer to the 954 datasheet on AEQ settings and registers.