Other Parts Discussed in Thread: DSI-TUNER
Hi,
We're having significant issues in getting LVDS output from our IMX8-module from Variscite. It has the SN65DSI84 mounted on the module. We can only measure on the LVDS side.
Attached below are display datasheet and two outputs from DSI Tuner (with and without test pattern enabled) together with yocto linux parameters for the DSI interface.
Test pattern works fine. LVDS clock is running at an OK frequency.
But we can't get any picture on the screen when test pattern is disabled.
Reading register 0xE5 gives either 0xC1 or 0x01 depending on the timing parameters.
As a sidenote we halso have a 7" single LVDS screen that can show picture (with and without test pattern) and still reports 0x01 from register 0xE5.
Questions
- How significant are these errors (PLL_UNLOCK, CHA_CRC_ERR, CHA_SYNCH_ERR).
- What conclusions can we draw from them? What to troubleshoot?
- Should we change anything in the Yocto DSI config, e.g. some of the flags that are needed?
- Any other ideas for troubleshooting?
Best regards
Christian
//===================================================================== // Filename : CSR_02_eg.txt // // (C) Copyright 2013 by Texas Instruments Incorporated. // All rights reserved. // //===================================================================== 0x09 0x00 0x0A 0x05 0x0B 0x10 0x0D 0x00 0x10 0x26 0x11 0x00 0x12 0x2f 0x13 0x00 0x18 0x6f 0x19 0x00 0x1A 0x03 0x1B 0x00 0x20 0x80 0x21 0x07 0x22 0x00 0x23 0x00 0x24 0x00 0x25 0x00 0x26 0x00 0x27 0x00 0x28 0xe1 0x29 0x03 0x2A 0x00 0x2B 0x00 0x2C 0x26 0x2D 0x00 0x2E 0x00 0x2F 0x00 0x30 0x03 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x29 0x35 0x00 0x36 0x00 0x37 0x00 0x38 0x00 0x39 0x00 0x3A 0x00 0x3B 0x00 0x3C 0x00 0x3D 0x00 0x3E 0x00 The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet
//===================================================================== // Filename : CSR_02_eg_pattern.txt // // (C) Copyright 2013 by Texas Instruments Incorporated. // All rights reserved. // //===================================================================== 0x09 0x00 0x0A 0x05 0x0B 0x10 0x0D 0x00 0x10 0x26 0x11 0x00 0x12 0x2f 0x13 0x00 0x18 0x6f 0x19 0x00 0x1A 0x03 0x1B 0x00 0x20 0xc0 0x21 0x03 0x22 0x00 0x23 0x00 0x24 0x38 0x25 0x04 0x26 0x00 0x27 0x00 0x28 0xe1 0x29 0x03 0x2A 0x00 0x2B 0x00 0x2C 0x26 0x2D 0x00 0x2E 0x00 0x2F 0x00 0x30 0x03 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x29 0x35 0x00 0x36 0x15 0x37 0x00 0x38 0x3d 0x39 0x00 0x3A 0x15 0x3B 0x00 0x3C 0x10 0x3D 0x00 0x3E 0x00 The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet
static const struct drm_display_mode lg_lm238wf1_mode = {
.clock = 54000,
.hdisplay = 1920,
.hsync_start = 1920 + 61,
.hsync_end = 1920 + 61 + 41,
.htotal = 1920 + 61 + 41 + 38,
.vdisplay = 1080,
.vsync_start = 1080 + 21,
.vsync_end = 1080 + 21 + 21,
.vtotal = 1080 + 21 + 21 + 3,
.vrefresh = 60,
};
static const struct panel_desc_dsi lg_lm238wf1 = {
.desc = {
.modes = &lg_lm238wf1_mode,
.num_modes = 1,
.bpc = 8,
.size = {
.width = 527,
.height = 296,
},
},
.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_HSE,
.format = MIPI_DSI_FMT_RGB888,
.lanes = 4,
};
