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DS90CR287: Data error at TxCLKOUT

na na78
Guru 16770 points
Part Number: DS90CR287
Other Parts Discussed in Thread: DS90CR288A,

Hi

The customer uses DS90CR287(TX) and DS90CR288A(RX).

FPGA supplies TxCLKIN.

When FPGA is heated (at Ta=55C), TxCLKOUT has jitters and it leads data errors.

Looking into TxCLKIN, there are little differences between at 25C and 55C but almost looks same.

I attached files.

support.xlsx

 

Actually, jitters at TxCLKOUT is disappeared with no error when TxCLKIN is formed correctly.

So the jitters at TxCLKOUT would cause of TxCLKIN.

Does the glitch of TxCLKIN around 1.5V level contribute to  jitters?

BestRegards

  • 0
    TI__Mastermind 35130 points
    Hello,

    The input clock doesn't look very clean to me. The region where the glitch happens is around the threshold level (0.8V to 2V; see the Electrical Characteristics table on page 4 of the datasheet) where the input switches from low to high. In this region the level is undefined so it's possible that contributes to the jitter. Do you know how many devices the customer is seeing this issue on? Are there any that don't have this issue?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 16770 points
    Hi I.K

    Thank you for your reply.

    The customer also understand the clock is not clean and it caused of jitters.
    They should condition the input clock.

    However, they are asking the following questions.
    Do you have reference data? It is OK not to be guaranteed.

    Q1.
    What is the input threshold voltage (slice level)?
    For example, would half of VCC be slice level?

    Q2.
    Can you tell the hold time for the device to be judged whether TxCLKIN is high or low at slice level? (If any)

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 35130 points
    Hello,

    Q1. Since it's 3.3V TTL/CMOS the input threshold voltage should be 1.5V
    Q2. Unfortunately I'm not sure about this point, as we don't have reference data for this.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 16770 points
    Hi I.K

    Thank you it is very helpful.

    They had one more question.

    1.
    What is the clock that latches TxIN0-27 by? TxCLK or internal PLL ?

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 35130 points
    From Figure 10 in the datasheet I believe it is the TxCLK.

    Regards,
    I.K.