• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 33 subscribers
  • Views 920 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLK10031: Link Error

Sadanori Kato
Guru 36540 points
Part Number: TLK10031
Other Parts Discussed in Thread: TLK10034

Hi,

Once link training has completed, the 10G-KR data path is enable but the link is lost on one of the test boards when the power supply is turned on and off repeatedly.
Looking at the difference between OK and NG, it seems that the eye pattern was fail, didn't open enough, so there seems to be a problem with the parameters obtained by link training.
Could you please tell me how to improve this issue ?

The important register settings are shown as below.

HS_SERDES_CONTROL_1 (register: 0x0002) (device address: 0x1E) ---> 0x831C
HS_SERDES_CONTROL_2 (register: 0x0003) (device address: 0x1E) ---> 0xA848
HS_SERDES_CONTROL_3 (register: 0x0004) (device address: 0x1E) ---> 0x7500

The addresses with different register values for OK and NG are as below.

HS_STATUS_1 (register: 0x0016) (default: 0x0000) (device address: 0x1E)
KR_FEC_C_COUNT_1 (register = 0x00AC) (default = 0x0000) (device address: 0x01)
KR_VS_RX_CTC_INSERT_COUNT (register = 0x8017) (default = 0xFFFD)

Best regards,
Kato

  • 0
    TI__Guru 64326 points
    Kato,

    In this case tuning the Serdes control registers while monitoring the HS error register will help to tune TLK10031.

    HS_ERROR_COUNTER (register: 0x0010) (default: 0x0FFFD) (device address: 0x1E)

    You mentioned different values for certian registers in the OK and NG cases, what are these values? I do not think you posted them.

    Also could you describe the " the power supply is turned on and off repeatedly" a bit more? Does your entire board get powered down or just TLK10031? Could you describe your application more so that I have a better understanding?
  • 0 in reply to Malik Barton57
    Guru 36540 points

    Hi Malik-san,

    Thank you for your prompt reply.

    For HS_ERROR COUNTER(register: 0x0010), this register value is 0x0000 legardless the link training is OK or NG.
    However, it is a register dumped result, so I do not know if it is correct or not.

    The different values are shown as below.
    However, the register values after link training aren't the same each time.

    - HS_STATUS_1 (register: 0x0016) (default: 0x0000) (device address: 0x1E)
      - OK case : 0xC037 or 0xF037
      - NG case : 0xC014 or 0xF012

    - KR_FEC_C_COUNT_1 (register = 0x00AC) (default = 0x0000) (device address: 0x01)
      - OK case : 0x0000
      - NG case : 0x0001

    - KR_VS_RX_CTC_INSERT_COUNT (register = 0x8017) (default = 0xFFFD)
      - OK case : 0xFFFF or 0xA54E or 0xC06F
      - NG case : 0xFFFF or 0x96E4 or 0xAABB

    The entire board get powered up and powered down repeatedly, so the opposite device of TLK10031 is also mounted on the same board.
    In addition, the pcb trace between the opposite device and TLK10031 is short.

    Could you please tell me the root cause and workaround ?
    Please contact me as I could share the eye pattern via a private message on e2e if necessary.

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Guru 64326 points

    Kato,

    You would need to check HS_ERROR COUNTER while data is being transmitted for a accurate reading.

    Another method for debug for this is to use TLK10031 loop back modes. I recommend using the Shallow local and Deep remote loop back modes in order see whether the HS or LS side of the device has a good link. This seeting is controlled by LOOPBACK_TP_CONTROL (register: 0x000B) (default: 0x0D10) (device address: 0x1E). More information on these modes can be found in TLK10034 datasheet section 5.3.1.17. 

    KR_FEC_C_COUNT_1 should be read in conjunction with KR_FEC_C_COUNT_2 to get the correct 32 bit counter value of the FEC corrected blocks counter.

    Are the inputs on the LS side AC coupled? What mode is the device in, 10GBASE-KR, General Purpose SERDES or a different mode? Does you application use a optical module? Could you provide a block diagram of your application? 

  • 0 in reply to Malik Barton57
    Guru 36540 points

    Hi Malik-san,

    Thank you for the comment.

    I have already sent the detailed information to you via a private message on e2e, so could you please check it ?

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    Guru 36540 points

    Hi Malik-san,

    I found that the difference in register settings between OK case and NG case, so this issue will be closed.

    I greatly appreciate your cooperation.

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Guru 64326 points

    Kato,

    Could you describe the major difference found between register settings of the OK and NG cases for others who may find this post useful? 

  • 0 in reply to Malik Barton57
    Guru 36540 points

    Hi Malik-san,

    The HS_EQPRE[2:0] register value was 111b(EQ disabled mode) in the NG case.

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Guru 64326 points
    Kato,

    Thank You!