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Original question:

XIO2001: Power-down sequence in PCIR=3.3V case

XIO2001: How to realize power sequence

Oba
Genius 17695 points

Part Number: XIO2001

Hello,

 

Do you have any reference design or something example circuit to satisfy these power supply sequence requirement with the case that is powered from 3.3V or 12V of PCIe x1 connector?

 

When generating PCIR(5V) and 1.5V from this connector 3.3V, it is difficult to satisfy power down sequence, PCIR have to be removed to 0 before 3.3V/1.5V. 

When generating PCIR(5V), 3.3V and 1.5V from this connector 12V, REFCLK is active before 3.3V is stable (REFCLK have to be less than VDD+0.5V).

I’m struggling how to solve these problems.

 

Regards,

Oba

  • 0
    TI__Guru 64326 points
    Oba,

    Other than the EVM schematic which if located in the EVM users guide on ti.com, we do not have any other reference schematic that is publicly available.

    Are you having trouble with power or power down sequencing? In order to help with timing I would look at the decoupling capacitance on the Dc voltage rails. there amy be some room to adjust values thus adjusting the time until the rail is stable. Please also consider the power rail noise as if the decoupling capacitance is too large it could not be filtered out and impact the performance of XIO2001.