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I am also not famillar with CEC. I've tried to do some searches for this but have not found anything which shows physical layers or a set protocol.
I have seen customers use this device to interface with their HDMI DDC line.
My thoughts:
This buffer still uses an open drain architecture for both sides.
1) The I2C side has a static voltage offset of about 700~800mV so any device interfacing with this device needs to be able to accept ~800mV as a logic low.
2) Devices interfacing to the I2C side of the device also should be open drain and not push pull
3) This device is meant to be used in pairs (2 P82B96s) and is an ideal solution for cable transmission. Frequency limited to 400kHz
If the HDMI CEC lines support (1) open drain, (2) accept 800mV as a logic low, (3) speed does need exceed 400kHz then this device should work.
