DS90UB913A-Q1: Link is not getting established between SER and DES

Rajan,
Is the LOCK signal going high? You can check the parity bit for forward channel errors and CRC for back channel error.

You can also use BIST mode to verify the link between Ser and Des. Also ensure the power supplies are ramped up and stable at the required operating levels before issuing PDB to reset the device. The datasheets cover the required powerup sequence.
Please refer to the DS90UB913A/914A datasheets for additional details.

You can also refer to the debug/diagnostics video module and the ALP module we have on the FPD-Link Learning Center link below on the web.

In certain fault condtion as per requirement it is expected to RESET the microcontroller. In this scenario I see 3.3V powersupply is not going to zero completly and returns from 0.8V to 3V3 again. In this situation SER 913 became unresponsive and we can not establish the link with DES. This situation not recover even if we try to toggle PDB pin of SER to reset it.

If 3v3 supply goes normal to zero then issue not occur. Because of hardware constraint we cannot make 3V3 go to zero in a specific conditions where we are facing this issue.

In below waveform You can UG3v3 of SER is not going to exact zero but immediately returning to 3v3.

Thanks Palaniappan Manickam, Please check my other post where I have explained situation in which link failed to established.

Hello,

Thanks for you reply,

I am attaching one more diagram which include only SER related power supply signals to avoid the confusion.

Below are the steps when issue generated-

1) SER is on and connected to DES >> working/Normal condition

2) Glitch occurs on power supply as per below waveform.

As per my understanding, 3.3V supply of SER is not going to zero completely and remain at 0.64V from where it is returning to 3.3V again and causing the problem. Since in software this glitch is not

controllable  I wanted to know if any solution for this?

During power-down, it is recommended to bring PDB low first before powering down the supplies (from the scope shot it looks like it is simultaneous). You can refer to this other thread on power-down:

>> I dont see any role of PDB if turned off before VDDIO, I already tried that I will show you waveform tomorrow.

If the issue occur because of glitch above I already tried PDB to turned down and up for 1 second in stable VDDIO and VDDN condition, but SER remain in same situation where it fail to establish the link.

How is the PDB controlled? Is that on software through a microcontroller/processor or through hardware with a RC filter network? Once the supplies are powered back up completely to the stable levels, have you tried issuing PDB pulse (H->L->H)?

I assume when you say the link is unresponsive you are monitoring the LOCK from the deserializer 914A, correct? In the 914A datasheet we have the recommendation for what to do on the deserializer side when the ser/des are not initialized in the proper order. Refer to page 51.

Hello,
It's been a few weeks. Not sure if you need any further support but you can always create a new thread.