• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 32 subscribers
  • Views 294 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS110DF111: DS110DF111

DS110DF410: DS110DF111

Andrzej Hadas
Prodigy 140 points
Part Number: DS110DF410

Hello.

My question is about DS110DF410  ADDR_0 - ADDR_3 pins

Do this  inputs  have defaults state without being connected to GND/VDD on POWER_UP when the I2C address is read or do this pins have to be connected to GND or VDD (via resistor).

In another words will this pins be read as HIGH or LOW on POWER  if left floating ?

Thank you.

Andrzej

  • 0
    TI__Guru* 92230 points
    Hi Andrzej,

    These pins are shared with lock indications which are true on high. So I believe these pins are in low state (i.e address 0x30).

    Regards,,nasser
  • 0
    Prodigy 140 points
    Hello Nasser.
    Thank you for your replay.
    If I understand correctly, the pins which will be left floating (ADDR_0, ADDR_1, ADDR_2, ADDR_3 ) will be read as LOW during power-up.
    What is recommended value of the pull-up resistors ?
    Is this documented somewhere in the ds110df410.pdf or in any other documentation ?
    We have 6 device on the same bus and if we can live some of them floating that would be a big space saving for our design.
    Another issue - since there is 16 I2C address available and we only need 6 different addresses do this addresses have to be sequential (0x30, 0x32, 0x34, 0x36, 0x38, 0x3A) or can this address be random). This devices will read configuration from a single EEPROM.
    Thank you.
    Andrzej
  • 0 in reply to Andrzej Hadas
    Prodigy 140 points
    Hello Nasser.
    Thank you for your replay.
    If I understand correctly, the pins which will be left floating (ADDR_0, ADDR_1, ADDR_2, ADDR_3 ) will be read as LOW during power-up.
    What is recommended value of the pull-up resistors ?
    Is this documented somewhere in the ds110df410.pdf or in any other documentation ?
    We have 6 device on the same bus and if we can live some of them floating that would be a big space saving for our design.
    Another issue - since there is 16 I2C address available and we only need 6 different addresses do this addresses have to be sequential (0x30, 0x32, 0x34, 0x36, 0x38, 0x3A) or can this address be random). This devices will read configuration from a single EEPROM.
    Thank you.
    Andrzej
  • 0 in reply to Andrzej Hadas
    TI__Guru* 92230 points

    Understanding EEPROM Programming for 10G to 12.5G Retimers_10-8-2015.pdfHi Andrzej,

    1). Normally there is a weak pull up or down on LVCMOS inputs or outputs. Please note leakage current mentioned in parametric table of the data sheet.

    2). You can use 1K-Ohm pull up or pull down for ADDR0 through ADDR3. This is the values we've used for the evaluation board.

    3). Addresses don't need to be sequential but this depends on how you would program register settings for each device in EEPROM. Please attached note a document describing this in more details.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 140 points
    Hello Nasser.
    I was hoping for reinforcement of your statement:
    "These pins are shared with lock indications which are true on high. So I believe these pins are in low state (i.e address 0x30). "
    When you say "I believe" makes me think that this may not be correct in all cases.
    We would like to have SMB address pins that should be read as "LOW" floating.
    Can you provide strong statement or can you point us to any documentation clarifying this issue ? This could be a schematic of relevant circuitry or a firm statement.
    Thank you and best regards.
    Andrzej
  • 0 in reply to Andrzej Hadas
    TI__Guru* 92230 points
    Hi Andrzej,

    The reason I said "I believe" is because all of our boards and evaluations have used either pull-up or pull-down on these pins. My suggestion is to use pull down or pull ups on these pins since this method is more noise immune. Also, these pins are LVCMOS pins and have two levels (either low or high).

    Regards,,,nasser