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SN65DSI84: Display Issue

CK Ho
Expert 1780 points
Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Dear Sir,

Our customer is using SN65DSI84 and encounter a problem.

The display color is not as expected.

This is the original picture:

But the display show as below:

Do you have any experience about it?

Can we set registers to modify it?

Or it should be tuned by video source?

Thank you very much

  • 0
    TI__Mastermind 35130 points
    HI CK Ho,

    Can you send the display datasheet and the .dsi file from the DSI-Tuner that was used to configure the register settings?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Expert 1780 points

    Dear I.K.,

    Belows are the datasheet and the register settings:

    G156XW01 3.pdf

    G215HVN01 1.pdf

    Fullscreen 15.6inch_setting.txt Download 
    //- 15.6 inch, For 1366 x 768
/*Dmesg from kernel*/
jht_8mq:/ # dmesg |grep DSI84-I2C
[    2.786214] DSI84-I2C: read 0x00  - 0x35
[    2.787145] DSI84-I2C: read 0x0d  - 0x00
[    2.788075] DSI84-I2C: read 0x0a  - 0x05
[    2.789012] DSI84-I2C: read 0x0b  - 0x10
[    2.789946] DSI84-I2C: read 0x10  - 0x20
[    2.790875] DSI84-I2C: read 0x18  - 0x78
[    2.791805] DSI84-I2C: read 0x1a  - 0x03
[    2.792749] DSI84-I2C: read 0x20  - 0x56
[    2.793680] DSI84-I2C: read 0x21  - 0x05
[    2.794614] DSI84-I2C: read 0x22  - 0x00
[    2.795547] DSI84-I2C: read 0x23  - 0x00
[    2.796479] DSI84-I2C: read 0x24  - 0x00
[    2.797407] DSI84-I2C: read 0x25  - 0x03
[    2.798329] DSI84-I2C: read 0x26  - 0x00
[    2.799249] DSI84-I2C: read 0x27  - 0x00
[    2.800170] DSI84-I2C: read 0x28  - 0x21
[    2.800866] DSI84-I2C: read 0x29  - 0x00
[    2.801798] DSI84-I2C: read 0x2a  - 0x00
[    2.802729] DSI84-I2C: read 0x2b  - 0x00
[    2.803662] DSI84-I2C: read 0x2c  - 0x00
[    2.804595] DSI84-I2C: read 0x2d  - 0x00
[    2.805528] DSI84-I2C: read 0x2e  - 0x00
[    2.806459] DSI84-I2C: read 0x2f  - 0x00
[    2.807392] DSI84-I2C: read 0x30  - 0x00
[    2.808321] DSI84-I2C: read 0x31  - 0x00
[    2.809250] DSI84-I2C: read 0x32  - 0x00
[    2.810173] DSI84-I2C: read 0x33  - 0x00
[    2.811093] DSI84-I2C: read 0x34  - 0xc8
[    2.812017] DSI84-I2C: read 0x35  - 0x00
[    2.812870] DSI84-I2C: read 0x36  - 0x00
[    2.813790] DSI84-I2C: read 0x37  - 0x00
[    2.814710] DSI84-I2C: read 0x38  - 0xc8
[    2.815631] DSI84-I2C: read 0x39  - 0x00
[    2.816554] DSI84-I2C: read 0x3a  - 0x00
[    2.817475] DSI84-I2C: read 0x3b  - 0x00
jht_8mq:/ #

//-15.6 inch, For 1366 x 768
/*Set the registers on driver*/

/* Soft reset and disable PLL */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_SOFT_RESET, 0x01);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_PLL_EN, 0x00);

/* four DSI lanes with single channel*/
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_CFG, 0x20);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_EQ, 0x00);

/* set DSI clock range */

i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_DSI_CLK_RNG, 0x2e);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_DSI_CLK_RNG, 0x00);
	
/* set LVDS for single channel, 24 bit mode, HS/VS low, DE high */	
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_LVDS_MODE, 0x78);	

/* x resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_LO, 0x56);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_HI, 0x05);

/* x resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_HI, 0x00);

/* y resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_HI, 0x03);

/* y resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_HI, 0x00);

/* SYNC delay high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_LO, 0x21);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_HI, 0x00);

/* SYNC delay high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_HI, 0x00);

/* HSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_HI, 0x00);

/* HSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_HI, 0x00);

/* Horizontal BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_BACKPORCH, 0xC8);

/* Horizontal BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_BACKPORCH, 0x00);

/* Vertical BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_BACKPORCH, 0x26);

/* Vertical BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_BACKPORCH, 0x00);

/* Horizontal FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_FRONTPORCH, 0x00);

/* Horizontal FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_FRONTPORCH, 0x00);

    Fullscreen 21.5inch_setting.txt Download 
    //- 21.5 inch,  For 1920 x 1080
/*Dmesg from kernel*/
jht_8mq:/ # dmesg |grep DSI84-I2C
[    2.762404] DSI84-I2C: read 0x00  - 0x35
[    2.763336] DSI84-I2C: read 0x0d  - 0x00
[    2.764266] DSI84-I2C: read 0x0a  - 0x05
[    2.765203] DSI84-I2C: read 0x0b  - 0x10
[    2.766137] DSI84-I2C: read 0x10  - 0x26
[    2.767067] DSI84-I2C: read 0x18  - 0x6c
[    2.767998] DSI84-I2C: read 0x1a  - 0x03
[    2.768934] DSI84-I2C: read 0x20  - 0x80
[    2.769864] DSI84-I2C: read 0x21  - 0x07
[    2.770796] DSI84-I2C: read 0x22  - 0x00
[    2.771729] DSI84-I2C: read 0x23  - 0x00
[    2.772662] DSI84-I2C: read 0x24  - 0x00
[    2.773590] DSI84-I2C: read 0x25  - 0x00
[    2.774510] DSI84-I2C: read 0x26  - 0x00
[    2.775431] DSI84-I2C: read 0x27  - 0x00
[    2.776352] DSI84-I2C: read 0x28  - 0x1f
[    2.777039] DSI84-I2C: read 0x29  - 0x04
[    2.777961] DSI84-I2C: read 0x2a  - 0x00
[    2.778882] DSI84-I2C: read 0x2b  - 0x00
[    2.779805] DSI84-I2C: read 0x2c  - 0x0f
[    2.780728] DSI84-I2C: read 0x2d  - 0x00
[    2.781658] DSI84-I2C: read 0x2e  - 0x00
[    2.782588] DSI84-I2C: read 0x2f  - 0x00
[    2.783519] DSI84-I2C: read 0x30  - 0x06
[    2.784449] DSI84-I2C: read 0x31  - 0x00
[    2.785384] DSI84-I2C: read 0x32  - 0x00
[    2.786316] DSI84-I2C: read 0x33  - 0x00
[    2.787246] DSI84-I2C: read 0x34  - 0x2f
[    2.788179] DSI84-I2C: read 0x35  - 0x00
[    2.789105] DSI84-I2C: read 0x36  - 0x00
[    2.790025] DSI84-I2C: read 0x37  - 0x00
[    2.790947] DSI84-I2C: read 0x38  - 0x2f
[    2.791868] DSI84-I2C: read 0x39  - 0x00
[    2.792791] DSI84-I2C: read 0x3a  - 0x00
[    2.793655] DSI84-I2C: read 0x3b  - 0x00


//-21.5 inch, For 1920 x 1080
/*Set the registers on driver*/ 
/* Soft reset and disable PLL */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_SOFT_RESET, 0x01);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_PLL_EN, 0x00);

/* four DSI lanes with single channel*/
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_CFG, 0x26);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_EQ, 0x00);

/* set DSI clock range */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_DSI_CLK_RNG, 0x2D);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_DSI_CLK_RNG, 0x00);

/* set LVDS for single channel, 24 bit mode, HS/VS low, DE high */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_LVDS_MODE, 0x6C);

/* x resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_LO, 0x80);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_HI, 0x07);
		
/* x resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_HI, 0x00);

/* y resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_HI, 0x00);

/* y resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_HI, 0x00);

/* SYNC delay high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_LO, 0x1F);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_HI, 0x04);

/* SYNC delay high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_HI, 0x00);

/* HSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_LO, 0x0F);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_HI, 0x00);

/* HSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_LO, 0x06);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_HI, 0x00);

/* Horizontal BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_BACKPORCH, 0x2F);

/* Horizontal BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_BACKPORCH, 0x00);

/* Vertical BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_BACKPORCH, 0x00);

/* Vertical BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_BACKPORCH, 0x00);

/* Horizontal FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_FRONTPORCH, 0x00);

/* Horizontal FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_FRONTPORCH, 0x00);

  • 0 in reply to CK Ho
    TI__Mastermind 35130 points

    Hi CK Ho,

    Please fill out your settings for each panel in the DSI-Tuner tool and then send the .dsi file to me or post screenshots of each window. It will be a lot faster than individually going through each register from the .txt files you sent.

    Regards,
    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Expert 1780 points

    Dear I.K.,

    Belows are DSI setting:

  • 0 in reply to CK Ho
    TI__Mastermind 35130 points

    Hi CK,

    The DSI settings look okay except for the DSI CLK. I believe 228MHz is too slow for the 1920x1080 panel and will result in a line time mismatch. Please try with the below settings instead:

    The DSI CLK needs to be 456MHz, and the divisor needs to be 6.

    Regards,

    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Expert 1780 points

    Dear I.K.,

    We set the DSI CLK to 456MHz, and the divisor configure to 6, but it does not work, the panel shows black screen.

    The setting as below:

  • 0 in reply to CK Ho
    TI__Mastermind 35130 points
    Hi CK,

    Are you following the initialization sequence in the datasheet? Please go through the debug section of this guide: www.ti.com/.../slla356.pdf

    And you can also watch this video: www.youtube.com/watch

    Regards,
    I.K.