DS8921: Pull-up, pull-down and terminator resistors in line.

Brandon, 

It is generally a good idea to use termination resistors on network data lines.  The 200ft (60m) cable length can create a reflective stub depending on the pulse width of the driver, even if the pulse happens only once per 2ms.  

We generally recommend termination resistors, one on each end of the bus.  So for your application, it would be good to put a termination resistor close to the driver that is pulsing, and one more resistor close to one of the receivers on the other end.  120 ohms of termination resistance is a typical value, giving an effective resistance of 60 ohms of load on the bus lines.

Best Regards,

Max Megee

INT-TRX Applications

Max Megee,

I have added the 120 ohm resistor on the drive pair and a 120 ohm resistor of each receive pair. In our case we have one driver, driving three recevive lines.

We found that the voltage swing is reduced greatly with the addition to more recieve pairs.

The chips are located on seperated systems. We are synchronizing the systems together so they do stuff together at the same time.

Current Setup (Problem Voltage swing on driver lines greatly reduced 1.2V to 2.4 V):

Driver Chip   ------(200 feet cable)----- Recevier Chip

Chip 1 Driver (120 ohm)  ----------> Chip 1 Reciever (120 ohm)

                                              ----------> Chip 2 Reciever (120 ohm)

                                              ----------> Chip 3 Reciever (120 ohm)

Chip 2 Driver Terminated (not used)

Chip 3 Driver Terminated (not used)      

Should the setup be the following:

Driver Chip   ------(200 feet cable)----- Recevier Chip

Chip 1 Driver (120 ohm)  ----------> Chip 1 Reciever (360 ohm)

                                              ----------> Chip 2 Reciever (360 ohm)

                                              ----------> Chip 3 Reciever (360 ohm)

That way the driver pair would see a 120 ohm termination resistor (3x360ohm in parallel = 120 ohm)

Chip 2 Driver Terminated 120 ohm (not used)

Chip 3 Driver Terminated 120 ohm (not used)    

Thanks,

Brandon

Hi Brian,

Good questions.  I think I've got a better picture of your setup now.  In your case, I would recommend that you only need to terminate one of the receiving nodes.  If your receiving nodes are daisy-chained together, then you should put a 120-ohm resistor on the receiver node that is furthest down the bus.  If the receiving nodes have a star configuration, then you should put one 120-ohm resistor on the receiving node that has the longest stub from the star point.  See below:

Case 1: Daisy Chain Receivers

Chip 1 Driver ---------(200 feet of cable)---------------Chip 2 Receiver (no term)----------Chip 3 Receiver (no term)---------Chip 4 Receiver (120-ohm)

Case 2: Star Receivers

Chip 1 Driver --------(200 feet of cable)--------- Connecting Point

------------->Chip 2 Receiver (no term)

------------->Chip 3 Receiver (no term)

------------->Chip 4 Receiver (120-ohm, if this receiver has the longest stub from the connecting point).

Does this make sense?  I know I mentioned a second terminating resistor in my previous reply, but you will only need that for a case when Chip 1 needs to use its receiver.  Then you would connect a 120-ohm resistor across Chip 1's receiver inputs.  You won't need a termination resistor close to the driver outputs. This setup should help the signal amplitude to return to normal levels.

Max

full setup:

Chip 1 Driver ---> (100 feet cat 6 cable) ---> Box at the base/bottom of pole ---> (100 feet cat 6 cable; back up the pole to chip 1) ----->   Chip 1 Receiver 

                                                                                                                        ---> (100 feet cat 6 cable; back up the pole to chip 2) ----->   Chip 2 Receiver 

                                                                                                                        ---> (100 feet cat 6 cable; back up the pole to chip 3) ----->   Chip 3 Receiver 

We have to use the same termination resistance for each chip due to manufacturability concerns. 

Good Example:

Chip 1,2,3 Driver 120 termination impedance 

Chip 1,2,3 Receive 120 termination impedance

OR

Chip 1,2,3 Driver 120 termination impedance 

Chip 1,2,3 Receive 360 termination impedance.

Example that wouldn't work for our requirements:

Chip 1  Driver 120 termination impedance, chip 2 no impedance, chip 3 no impedance

Chip 1 Receive 120 termination impedance, chip 2 no impedance, chip 3 no impedance

Hopefully this description gives you a better picture of the setup. 

Brian,

There isn't going to be an ideal situation in this case, since the network is configured as a star network with long cable lengths to each node.  You may try to "partially" terminate each node, as you have suggested above by using a larger value resistor for each node.  You can try a resistor value of (60 ohms * number of nodes), so in this case 60 ohms * 4 nodes = 240 ohms.  You can place a 240 ohm resistor close to the receiver inputs at each node in order to partially terminate the network.  You will still get some reflections on each end of the line, but hopefully their magnitudes will be lessened.  Using a transceiver with slower edge rates can also help to reduce the effects of reflection on signal integrity on the Bus.  

Max

Thanks for the help. 

I have another concern/question. I have the single end driver and single ended receiver (pins 2,3) going to an Artx7 FPGA. The only supported standards and voltage levels for the Artix 7 Xilinx FPGA are LVTTL,LVCMOS, etc., all of them are at 3.3 Volts.

DS8921 Pin 2 ---> FPGA I/O Bank (Input) LVTTL VCCO 3.3 Volts

DS8921 Pin 3 <--- FPGA I/O Bank (Output) LVTTL VCCO 3.3 Volts

I measured the single ended receive pin #2 to be 4 Volts floating.

I measured the single ended driver pin #3 to be 1.5 Volts floating.

When the IC and the FPGA are connected, the voltage is pulled down to roughly 3.6 Volts. The maximum rating for the FPGA I/O is 3.6 so I think the FPGA is pulling the voltage down.  

My question is will this damage the FPGA I/O pins? The datasheet for the DS8921 (page 10) says, Use TTL/LVCMOS logic levels at DI and RO. That statement to me says that pins 2 and pins 3 are LVCMOS compatible which should mean that it will not damage the FPGA pins but can you confirm?

Looking at the datasheet, Figure 6 shows that the DI pin is capable of processing input signals on a 3V supply rail.  What is unclear is the maximum output High voltage on the RO pin.  It only spec's a minimum output High voltage at 2.5V.  This part was released originally in 1998, so the datasheet information looks limited.

Since you mentioned that the micro runs on a 3.3V rail, you could measure the current coming out of the RO pin when RO is driving high.  You could make a call on whether or not damage may occur based upon the level of current that you see. 

Since the DI pin is capable of processing 3.3V signals, it stands to reason that the RO pin should also transmit across the 3.3V domain without signal integrity issues.  However, since the supply to the transceiver is 5V, I would just want to double check that you don't see high current draw out of the RO pin by the micro's 3.6V supply setting.  

I'll try and get some more information on this and get back with you with more details.

Max Megee

Brandon,

I wanted to check in on this with you once more.  From looking at the datasheet, it looks like the DS8921 device works ideally with a 5V TTL logic level.  However, you may be able to operate successfully without issue if the receiver output does not source too much current when the logic is regulated at 3.6V.  Were you able to take any current measurements from the DS8921 receiver output to the MCU's input logic?  

Best Regards,
Max Megee

Transceiver Applications

Max,

This part seems to work better, sn65lvds179. Since you know our configuration do you have any suggestion on termination resistors? The datasheet for this part says its made to drive a 100 ohm load so I was thinking 100 ohm for driver and 300 ohm for each receiver node (3 receive nodes). It seems to work with a 120 ohm at the driver and 360 ohm at each recevier but I think it could be better. 

Thanks,

Brandon

Max,

The 300 ohm at the receiver and no termination resistors for the drivers looks good. I'm not really sending "data" at any high rate. The signal integirty and speed seems to be sufficent.

There is one "mistake" with our wiring but it seems to not affect the performace of the chip (does invert the signal but that okay).

Current Wiring (1)

D- of chip1  connected to the R+ of chip1 , chip 2, and chip3

D+ of chip1 connected to the R- of chip1, chip2, and chip3

Is this okay? Or will this damage the chip? I didnt see anything about inverted vs noninverting wiring schemes in the datasheet

Or should the wiring be like below? (2)

D+ of chip1  connected to the R+ of chip1 , chip 2, and chip3

D- of chip1 connected to the R- of chip1, chip2, and chip3

Just to clarify, did you decide to implement the DS8921?  

I can't find anything to indicate that you will damage the device if you invert the wiring as you have described, since the bus voltage levels are symmetrical  for D+ and D-.  You will of course invert the received signal.  If you are okay with that, I don't see a danger to the functionality of the transceivers.  

Best Regards,

Max 

Max,

Nope, the DS8921 didn't work at the LV levels. We are going with the SN65LVDS179.

To calarify your previous response was for the SN65LVDS179 chip correct?

I will keep you informed about the chips performace once we put it out into the field.

Thank you.