DS90UB953-Q1: IS it possible to output clock signal (27MHz) for ISP on 953 side?

NY,

The CLK_OUT can be set by using this equation:

CLK_OUT = FC x M/(HS_CLK_DIV x N), where FC is the forward channel data rate, and M, HS_CLK_DIV, and N are parameters set by registers 0x06 and 0x07.

For a CLK_OUT = 27MHz, you can set:

HS_CLK_DIV = 16

M = 27

N = 250

The above values translate to 0x9B for Register 0x06 and 0xFA for Register 0x07. Because the M/N is a fractional divide ratio, there is expected to be about 4ns of jitter.

If you don't want jitter and are OK with a frequency that is 0.1% deviated (CLK_OUT = 27.02702703 MHz), then you can use these settings:

HS_CLK_DIV = 4

M = 1

N = 37

The above values translate to 0x41 for Register 0x06 and 0x25 for Register 0x07.

Best Regards,

Jonny