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DS90UB947-Q1: The timing requirement of power and register configurations when use DS90UB947-Q1 and DS90UB948-Q1 pair

Maka Luo
Intellectual 1125 points
Part Number: DS90UB947-Q1
Other Parts Discussed in Thread: DS90UB948-Q1,

Use DS90BU947-Q1 and DS90UB948-Q1 pair, at present, meet black screens and flower screens random. some questions on it.

Just now we provide power (3.3v) to DS90UB948-Q1 firstly, DS90UB947-Q1 no power on, but find VDDA have 1.1v voltage, it seems have power from 948 to 947 by FPD-Link line.

have below questions need your help:

1.The timing requirement  of power on and register configurations between the both

2.if first power on DS90UB948, how about the risk of VDDA 1.1v voltage of DS90UB947-Q1?

3. In datasheet PDB high threshold is 2.0v when VDDIO =3.3V, but actually test the PDB high threshold voltage is 2.3v, is it have any risk?  

  • 0
    TI__Mastermind 30515 points
    Make,
    you can use //helpme system for it.
    regarding the link between UB947 and UB948, only 3pins are used here. 2pins for diff. high speed signals, the 3rd pin is GND. for diff. high speed signal, it is AC coupling. so we can't understand why you have 1.1V offset in the UB947 side, it is out of our understanding.
    for the 3 issues:
    1.The timing requirement of power on and register configurations between the both
    --> pls follow up d/s design. also, no special reg. setting is required if NO remote i2c access is required. you can use the mode_sel pin to run up the UB947/UB948 system. If need more, please let's know the customer and project message in TI internal system.

    2.if first power on DS90UB948, how about the risk of VDDA 1.1v voltage of DS90UB947-Q1?
    --> sorry we can't understand this issue from chip level. it could be the system link issue?

    3. In datasheet PDB high threshold is 2.0v when VDDIO =3.3V, but actually test the PDB high threshold voltage is 2.3v, is it have any risk?
    --> pls follow up d/s design.


    regards,
    Steven