Other Parts Discussed in Thread: TCAN4550-Q1, TCAN1051
Hi,
My customer has designed in the TCAN1051GVDRQ1 and has a couple of questions coming out of reading the SLOA101b - TI CAN application note.
Would you be able to help with these questions?
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In Section 3.1.1 it says “CRC–The 16-bit (15 bits plus delimiter) cyclic redundancy check (CRC) contains the checksum (number of bits transmitted) of the preceding application data for error detection.” I read this to mean the CRC is only calculated on the data in the Data Field, is this correct? Or is the CRC also calculated on the Identifier Field i.e. over the whole message?
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Is the CANBus block in the micro typically implemented entirely as a HW state machine, or is it typically a controller running from ROM code in the micro?
Does TI have any recommendations for the application SW level protocol e.g. additional error detection and recovery strategies on top of what is already implemented in the CANBus system for critical data?
Thanks in advance.