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TL16C754B: IORn/IOWn datasheet "2P" MIN strobe width requirements T7w and T13w seem to be incorrect

Part Number: TL16C754B

I have legacy design with TL16C754B quad UART asynchronous interfaced to a microcontroller.  The design works fine, but the IORn/IOWn timing does not meet the data sheet pg. 19 T7w and T13w minimum strobe width specs. 

The design uses a 14.7456 MHz crystal on the TL16C754B XTAl1/XTAL2 pins, giving clock period P = 67.8 ns.  So page 19 quantity 2P = 135.6 ns should be the minimum strobe width to use.  However, the microcontroller interface uses a IORn strobe width of  94 ns ( and IOWn strobe width 128 ns), which is significantly less than the spec.  Yet, the interface has worked reliably for years.   

In order to experimentally determine how much margin there is in the design, I took an old board and modified the IORn strobe width down to as short as 32 ns ( IOWn down to 48 ns) and wrote/read test patterns to the UART scratch register.  I did 100,000+ iterations with no error.  According to the page 19 timing specs, this should not be possible since the 32ns pulse is less than half ot the crystal period.  

What am I missing?

Are the data sheet specs correct?  

Finally, I modified the the clocking of the TL16C754B by removing the crystal and using a square wave generator as a clock into the XTAL1 pin.  I tried square wave frequencies of 10 MHz down to 800 KHz and still saw correct performance of the asynchronous interface to the micro.

Is the bus interface of the TL16C745B really synchronous as described in the data sheet pg 19, or is it asynchronous, like the TL16C754C?  

This is not an idle question, it is potentially a reliability issue.  Thanks in advance.  -- Dave B

  • Hi David,

    Understood that it is important to clarify these specs for you to determine your design margin. We will look into these questions and get back to you early next week.

    Regards,
    Max
  • Hey David,

    I will try to reproduce what you are seeing with a ~1MHz clock and see if I am able to come up with the same thing.

    I've also contacted our design team to try to understand how the IOR/IOW circuitry works. From what you are describing, it sounds like the device does not rely on an external clock source to trigger IOR/IOW but either has an internal clock (I don't think it does) or simply uses falling/rising edge to clock in/out data.

    I will get back to you on this as soon as I can. It may take me some time to get a set up (need to find some equipment) going that how pulse IOW/IOR under a microsecond.

    Can you tell me what Vcc you are using this device at?

    Thanks,
    -Bobby

  • Hey Dave,

    I reached out to our design team to get their insight on this, however because the device is so old, we don't have the internal design of the device.

    Design Comments:
    I reviewed the datasheet, T12d indicates read data is available 30ns/47ns after IOR (bar) is asserted if the setup delay w.r.t CS is met. The design behavior is expected.

    My guess is the IOR strobe width may be critical for back to back reads or the read operation is asynchronous.

    Design Suggestion:
    You can run the following experiments to understand the behavior:

    1. Back to back reads (from different register locations) varying the IOR strobe width between 30ns to 2 clocks,
    2. Back to back reads (from different register locations) varying the IOR falling edge w.r.t clock (rising/falling)
    3. Back to back reads (from different register locations) varying the IOR rising edge w.r.t clock edge (rising/falling)
    ------------------------
    On my end, I tried to modify my 752B to test with however I ended up damaging it (does not like 5V). After looking at this I looked at 754B and found that the 2 devices seem to indicate different Vcc max voltages which indicate the devices either use a different process technology or have different IP inside. This essentially means the two devices could be different and testing the 752B may not be the same as testing the 754B. If this is the case, I do not have a board I am able to test with the 754B on my end. I will have to place an order online for an adapter board to DIP board to try testing the 754B. (I will check again with design to see if 752B and 754B can be compared to each other in this way)

    Thanks,
    -Bobby

  • Bobby -- Thanks for digging into this. In response to an earlier question, I run the TL16C754B at Vcc =3.3V. In response to the latest post, I will see if I can do the tests you enumerated, or something close to them, and let you know what I find.
  • Hi David,

    I just wanted to check in on this - have you had a chance to look any more into these tests?

    Regards,
    Max
  • I haven't had a chance to do these tests yet. I still plan to investigate this, perhaps in the next two weeks.
  • I have done a few tests which indicate the read/write interface is asynchronous.  Basically, I completely removed the crystal/clock from the TL16C754B entirely, and was still able to write/read registers with strobe pulses down to 30 ns ( I didn't try shorter than this ).   I was able to write patterns to the scratch (SPR) register and the DLH register and read them back with no issues.  The minimum time between these "back to back" reads was around 200ns in these tests.  Everything looked good.  As far as I can tell, the interface is asynchronous.

  • Hey David,

    Thanks for getting back to us with your testing. I agree with you, if you are able to read and write through the parallel interface without a clock then the device is indeed the parallel interface is asynchronous while the serial data exchange is synchronous with the clock.

    Thanks,
    -Bobby