SN75DP130: Support Edp

Shu-Cheng

Please have 100k pulldown on HPD_SNK, otherwise the schematic looks ok.

Would you please share the failing report? What pattern did you send and did you change the DP130 SWING and Pre-emphasis setting?

Thanks
David

Hi David,

Sorry for missed fail report

Please refer as below

Shu-Cheng

Are you disabling link training in DP130 and manually set the equalizer, output VOD, and pre-emphasis level?

Are you also using the eDP compliance fixture to do the test?

Thanks
David

Hi Sirs,

Our schematic on first floor of this topic.

Our are setting are default.

Looks we don't reserve I2C channel, right?

So do we need reserve I2C control at next schematic version?

We not sure do we disable link training? it's control by i2c?

We have try to pull high 3.3 v on DP_ADDR_EQ, we found input Voltage Swing and Pre Emphasis could change but the output always fixed, please refer as below

We think our schematic is ok ( you have checked before)

Our software is use ”DisplayPortApplet_v4.27_x64”

Thanks!!

Shu-Cheng

Since this is an eDP application, then the lane is fixed and will not change. Link training could be disabled for this application and all device configurations would need to be accomplished through I2C control. Through the I2C control, you will be able to configure lane by lane equalization, output Vod, pre-emphasis, as well as number of lanes, data rate.

For example, to write the TRAINING_LANE0_SET, DPCD register 0x00103h, use the following instructions.

Set up Lane 0 with 800 mV and 0 dB pre-emphasis, write a value 0x02 (DPCD_REG00103[1:0] = 10 for Voltage swing level 2 and
DPCD_REG00103[4:3] = 00 for Pre-emphasis level 0)

a. Write REG1c to 0x00
b. Write REG1d to 0x01
c. Write REG1e to 0x03
d. Write REG1F to 0x02 – this will write a 0x02 to the DPCD register 0x00103

Please also use eDP compliance test fixture and software for compliance test.

Besides need 100k pulldown on HPD_SNK, the schematic looks ok. I can also take a look at the layout if needed.

Thanks
David

Hi David,

Thanks for your quick reply.

We still have some questions.

1. What is mean since this is an eDP application, then the lane is fixed and will not change? so output be fixed is edp Channel characteristics?

2. Usually, to enable Link training is right? so how could we enable link training?

3. Why our DP130 output always be fixed around 250mV whether the input is 350mv or 180mv?

4. Our test GUI as below, could you help check which setting is suitable for us?

Shu-Cheng

In a typical DP application, DP130 output would connect to a DP connector and the DP cable length will change. But in a typical eDP application, DP130 output is permanently connected to the eDP panel, so the trace length between the DP130 and eDP is fixed and will not change.

Knowing the trace length is fixed, then it is possible that the link training can be disabled through I2C control and DP130 EQ, Pre-emphasis, and VOD can be manually set base on the fixed trace length. Link training is enabled by default, but can be disabled using I2C.

DP130 has its own TX VOD (amplitude) and pre-emphasis level. The amplitude being set by the GPU will not be sent by DP130. DP130 will send the signal with its own TX VOD and pre-emphasis. This is why I am asking to disable the link training, and manually set the DP130 VOD and pre-emphasis and see if a particular setting will pass the eDP compliance test.

Thanks
David