DP83867IR: Input Clock Specifications

high speed guy

Part Number: DP83867IR

Hello,

In design with the DP83867 Ethernet Phy and have a question about the input clock for the device. We are using a single ended LVCMOS 25MHz clock connected to pin 19. The datasheet does not specify the electrical requirements/properties for the XI/XO pins and we are wondering if that information is available. More specifically, we would like to verify that we can use a 1.8V LVCMOS clock for that input even though we have VDDIO set to 3.3V.

Thank you,

HSG

over 6 years ago

0 Ross Pimentel over 6 years ago

TI__Mastermind 23675 points

Hi HSG,

For the DP83867IR clock requirements, please see page #111.

0 high speed guy over 6 years ago in reply to Ross Pimentel

TI__Expert 3505 points

Ross,

Thank you for the reference page. It is helpful. However, specifically I would like to now verify that I can use the 1.8V clock input per the instructions on page 111 in the data sheet and that using VDDIO set to 3.3V has no barring on this choice for the clock input voltage.

Thanks,
HSG

0 Ross Pimentel over 6 years ago in reply to high speed guy

TI__Mastermind 23675 points

Hi HSG,

You can use 1.8V clock to XI without a cap divider when VDDIO is 3.3V.

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DP83867IR: Input Clock Specifications