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CCS/DS90UB902Q-Q1: DS90UB902Q decode data LOCK is all low

user5110132
Expert 1950 points
Part Number: DS90UB902Q-Q1

Tool/software: Code Composer Studio

Hi

I design a circuit of DS90UB902 chip to decode the LVDS signal from the camera！

I select the camera mode which set the remote DS901 M/s = L; PDB = H; Res = L, 

The DS90UB902 configure is  M/s = H; PDB = H, Res = L, Bisten = L

and when set the weaken up signal to 901 

Then the status register of 0x1C  is 0x02, Which the Lock is L

I do not know why

  • 0
    Expert 1950 points

    The more information for this problem as follow

    The signal of the DS90UB902 Rin+ and Rin- as follow'

  • 0
    Expert 1950 points
    1. And the clock of pixel is 12MHz is just at the range of 10MHz and 43MHz;
    2. The peak mV bigger than the 180mv as the datasheet showed

    What is the reason to cause this problem???

    The lock pin is LOW all the time??
    It can not to lock the PLL
  • 0 in reply to user5110132
    TI__Genius 10475 points
    Hello,
    Please refer to the datasheet for the power up requirements and PDB pin and make sure the recommendations are followed.
    It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltages. An external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized.

    Both the serializer and deserializer have PDB input to enable or powerdown the device. When you toggle the PDB (1 -> 0 -> 1) what is the status of LOCK?